Oversees product development for various end markets in advanced process technologies. Leader in digital and mixed-signal design, IP and product development.

FPGA & MPSoC design and product development on Virtex, Kintex, Artix and Zynq product families.

• Project leader responsible for productizing Clustered Multi-Thread “Bulldozer” 32nm server processor core and successfully enabling product launch of Opteron server SOC by managing a multi-function 200+ member team comprising design, verification, architecture, platform and system debug. • Successfully led a multi-site 130+ member team in the design and development of the 32nm “Bulldozer” server core and “Piledriver” client core CPUs culminating in Opteron server SOC booting Windows within 3 days of package arrival. “Piledriver” core was targeted at Trinity Fusion APU. - Orchestrated tactical and strategic product life cycle & roadmap planning, execution and day-to-day operational management of high performance CPU design methodology for high frequency & performance, low power and platform scalability. Managed technical tradeoffs in various domains that included CAD, circuit & process technology, design methodology and integration leading to core IP delivery on time.• Started a new initiative within AMD evangelizing and setting up the SOC center of excellence in the areas of process technology, package, test and verification across all of SOC Processor projects to enable rapid execution by sourcing IPs across various sites and divisions.• Served as the focal point for strategic roadmaps for 45nm, 32nm SOC chips, socket compatibility, process variance working with product planning, marketing, server and client architecture teams.PRODUCTS: Athlon64, Opteron, Turion line (90nm, 65nm):• Successfully managed the delivery of the first dual core & single core processor on 65nm from RTL to tapeout in record time of 9 months. Boot-strapped dual-site (Boston & Sunnyvale) design capability managed a high performing multi site team of 50 engineers/technical leads. Enabled product introduction within 9 months from first tapeout, has now sold over 60 million CPUs.

Design and Development of Bluetooth and 802.11 Chipsets• Architected and implemented SOC circuit design and CAD methodologies for the first TrueRadioTM combo 802.11b and Bluetooth digital baseband and MAC chip on TSMC 0.18u process resulting in functional silicon on first tapeout. Drove silicon characterization, debug of functional yields, FA process and design correlation for volume ramp.• Successfully drove design porting and tapeout for the first product to a new foundry (Silterra) 0.18u process in record time of 2 months. This cost reduction exercise saved 20% of manufacturing cost on the baseband chipset.• Managed methodology and technical specs with foundry (TSMC), packaging (ChipPAC) and testing (Credence) vendors.

Design and Development of Pentium Pro, Pentium II, Pentium 4PRODUCTS: Pentium 4 (0.13u -2.2 GHz, 0.18u -1.8Ghz), Pentium II & Pentium Pro (0.5, 0.35, 0.25u)• Led an 8 person team in the vertical design of integer fireball execution unit on Pentium 4 (0.13u) towards a successful tapeout and product introduction. This was a key component in the high frequency NetBurst Architecture since it operated at twice the core clock frequency at 4.4 GHz.• Chaired a project task force on Dual Vt replacement techniques for domino circuits, Hot E degradation mechanism for full chip and proliferated the implementation of best practices across project team.• Drove the speed debug of high frequency paths on first silicon rev of Pentium 4 (0.18u), root caused early Si speed paths and implemented fixes to meet frequency goals for production within one year of tapeout. Responsible for the timing/noise/layout convergence of the execution engine for Pentium 4 revisions to a target of 1600 MHz.• Pioneered & productized the design and development of double pumped domino (ping-pong) design for the X86 flag generation unit which was used to replace self-resetting dynamic logic and saved 6 months in design time for the same performance. This was later proliferated through out the Pentium 4 design staff.• Designed memory store array and control block on Pentium II that exceeded functional and performance goals.• Performed standard cell library characterization and ported IO designs to 0.35 micron that met or exceeded frequency and performance goals. Key to product ramp of 0.35u Pentium Pro.