Brandon Schenck Email & Phone Number

Rochester, Mn, Us

Rochester, Minnesota, United States

Rochester, Minnesota Area

Marvell has completed acquisition of Avera Semi! This is an exciting step in our journey from IBM Microelectronics, which started with the GlobalFoundries acquisition in 2015 and then Averasemi last year, in preparation for this merger. We bring to Marvell a 25-year heritage of delivering leading solutions to silicon customers.I am currently a technical lead for customer ASIC programs in 14nm, 7nm, 5nm, and 3nm technologies.

Rochester, Minnesota Area

Design lead and customer engagement manager for ASIC solutions team at newly formed Avera Semiconductor, a new subsidiary of Globalfoundries. My ASIC solutions experience spans industries from wired and wireless infrastructure, AI and machine learning, aerospace and defense, and datacenter applications.

Rochester, Minnesota Area

Chip technical lead and Client Interface for ASIC Design Center in 14nm and prior technologies.

Rochester, Minnesota Area

Chip technical lead and Client Interface for IBM ASIC Design Center in 45nm, 32nm and 14nm technologies. Currently helping lead the technical effort to build the first IBM customer ASIC in 14nm (FX-14) technology.

Full design experience, including: logic design, DFT, timing analysis/closure, physical design and integration, power, simulation, logic synthesis, verificationExpertise in design of clock grid methodologies - fully integrated designs for low skew/low power clocks and complex synchronous designsFamiliar with 45nm, 32mn and 22nm technologies, both ASIC and Custom methodologies. Also helping define tool and methodology flows for 14nmDevelopment of custom processor clocking methodologies, including POWER systems. Experience with DDR, PCIE, SERDES and other I/O architectures.Clock lead for Microsoft XBOX 360 project, developing a custom gaming clock design; Clock lead for Bluegene/Q System, one of the fastest and most energy-efficient supercomputers in the worldFamiliar with IBM Design tools (ChipBench, Einstimer) and Cadence tools (Virtuoso, Finale, Encounter). Some exposure to Synopsys tool set, mainly Primetime and Design Compiler.Active in the IP and Patent Process - Author of multiple patent applications currently on file or issued with USPTO.IBM Rochester New Hire Network President and IBM Club Director - local climate initiatives.

Rochester, Minnesota Area

Hardware design engineer, focus on design-for-test logic and pervasive clocking structures. Supported multiple standard product and custom ASIC parts.

Rochester, Minnesota Area

Worked one co-op and 4 summer internships over the course of 5 years with the same hardware department at IBM. Supported both internal and external designs, focusing on ASIC clock and logic design with front- and back-end teams.Responsible for simulation and verification of multiple clock, test and self-test environments.Exposure to JTAG and Boundary Scan designs and the test and clocking structures.

Master Of Science, Electrical Engineering

Graduated with Honors

Bachelor Of Science, Computer Engineering

High School Diploma