Scott Applebaum Email & Phone Number

San Jose, California, Us

Engineering solutions for customer designs utilizing TCL and YAML for Flowtool and Flowtracer flows for the physical implementation using Innovus. Floorplaning and generating timing reports for RISC-V and ARM based CPUs. D2D on chip communications for autonomous vehicle AI processors. PD of Superconducting logic (RQL) for Quantum Computer Applications.

Costa Mesa, Ca, Us

Design specification of commercial Lutron systems for lighting control and Title-24 compliance.

San Diego, California, Us

Residential and Commercial Lighting and Controls Automation. IoT Product Development. Special automation project design, development, and programming.

San Diego, California, Us

Founded the company as a gateway to the development of patent and production of the PowerSTAR Performance Spark Plug.I designed, tested, funded, and built the product.Developed a semiautomated welding system for production. I designed an Arduino-based semi-custom manufacturing processing system utilizing an industrial real-time microcontroller based on the custom ATmega328P. The design allowed anyone with minimal training and no welding experience to achieve a perfect weld.Achievements:California Energy Grant Recipient- EISG Small Grant program Finalist in the 2009 Clean Tech Open for TransportationWinner of the CONNECT 2010 Most Innovative Product of the Year Award for Clean TechA graduate of the Connect Springboard 2011San Diego Business Journal 2012, 2013 Innovation Awards Finalist

EPS Corp. was a company I founded to bring Computer Automated Underground Car Parking Systems to the US market. I licensed the technology from Trevipark Limited. The system was designed and built in Italy. The company was bought by Mitch-Co in 2006 and became Perfect Park

Geneva, Switzerland, Ch

Technical Excellence Award and Company trade Secret Award: Developed at speed test screening algorithm for the iCore an ST20-C2 520Mhz R&D embedded SOC IP block.Verification Team Leader: Developed methodology and managed the verification team of SystemC/Verilog based Superscalar ARM hyperthreaded processor (used as a high-performance SRAM-based network packet search engine) using Specman e. IR&D iCore Verification Lead: Developed a dynamic memory initialization algorithm for functional verification and an effective address generator to ensure valid memory accesses. the iCore was a 520Mhz R&D embedded SOC synthesized IP block with eight-stage pipeline support to execute up to three instructions per cycle. The design operated up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core at the time.Physical Design: Developed back-end P&R flow using Astro for High Speed Domino logic of a DSP CORE Execution Unit.

Santa Clara, Ca, Us

Chief Architect for the largest High-speed Verilog synthesized SOC design. SONET/SDH OC-12 to OC-48 Mux/Demux. Developed High-speed SOC design methodology.SERDES, transmitter and receiver framers, LOF/OOF state machines. Simulated w/NC-Verilog.Wrote test programs to check the design to >95% fault coverage. Wrote software test specs for real-time lab verification and managed junior engineers and outside software, consultantSemi-custom cell circuit design and modifying. PSPICE simulation. digital modeling.Co-Developed 2 design utility patents; 6,493,359 and 6,463,847 assigned to Qualcomm. Managed a team of 7 Engineers during the 3 months manager absence, reporting to the VP Engineering and company President.

• Designed and consulted on numerous Deep Sub-micron networking SoCs.• Worked closely with customers developing and implementing ASICs from product specs to working silicon in high volume production.• Consulted on digital logic design, synthesis, floor planning, physical design, including place and route, and custom cell implementations.• Implemented semi-custom datapath design elements for high-speed throughput using datapath compiler in Compass tools.• Application engineering and customer support on both pre and post-sales.Design and Test activities utilizing Compass Design Tools included: • Chip architecture • VHDL/Verilog RTL coding • Synthesis • DFT, full scan and JTAG insertion • Schematic capture •Simulation • Static timing analysis • Test program generation • Fault grading • Semi-custom and gate-array physical design utilizing extensive floor planning • Place and Route • Custom block • SPICE • Scripting customization Layout design tools • RTL- GDSIII - Hardware acceleration and emulation using Ikos NSIM and VoyagerSome notable projects I worked on were for Viterbi Decoder for Hughes Networks -Direct TV STB, GI Cable Radio STB, DES Encryption chip VLSI Std Product, Tseng Labs ET4000 graphic chip, Newbridge Networks ATM processor, Worked with Dr. Feng-hsiung Hsu and Murray Campbell at IBM on the Deep Blue chess position processor chip that used the Alpha–beta pruning to beat the Grandmaster Kasparov in 1996. 480 of the chips were used and are on display at the Smithsonian - National Museum of American History!

Designed and verified 2 highly complex Dual DMA processors ASICs for a NAVY EMSP Program for P3 submarine detection. Used Bell Labs internal design tools on Sun workstations: schematic capture, logic synthesis, timing analysis, and fault simulation. Wrote Unix shell and C programs to automate key design tools.

Developed Satellite flight computer systems for DMSP, Landsat, and The Mars Observer. Rad Hard ASIC design gate array Memory Error Detection and Correction ASIC using Modified Hamming Code on dual 32-bit bus CPU. One of the first design engineers to use LSI Logic Design tools (LDS) on Sun workstations. IR&D MIL-STD-1750A flight computer boards and memory system. Tested and debugged ground test equipment for the SCP-234. My flight computer designs are some of the few space hardware that went to Mars.