Scott Appleton Email & Phone Number

Harvest, Al, Us

Huntsville, Al, Us

Huntsville, Al, Us

Supervised engineers and technicians responsible for manufacturing test of ADTRAN's carrier network xDSL, LPU, and cell-site fiber product lines. Supported Operations both locally and at Tier 1 contract manufacturers overseas.Responsible for organizing and deploying test equipment to contract manufacturers in Mexico, Vietnam, and China. Served as point-of-contact for engineering issues. Provided real-time support across multiple time zones as required, including remote interaction using VNC. Provided on-site technical support at contract manufacturers for new product introductions.Interfaced with multiple engineering and manufacturing groups to release products on schedule. Worked directly with engineers, line supervisors, and test operators to improve first pass yield (FPY).Associate architect for the functional test platform responsible for testing nearly all ADTRAN products. Developed core library code in C++ using Eclipse, MinGW, and the wxWidgets and Boost libraries for portability between Windows and Linux. Helped plan new capabilities for the platform.

Huntsville, Al, Us

Lead Test Design Engineer for carrier network DDS products. Responsible for creating and maintaining test applications for a high-volume, high-mix production environment. Developed functional tests to run single-up on ADTRAN’s custom FACTS stations, both in-house and at contract manufacturers. Designed personality modules and standalone stations to support testing of new products. Designed and built multi-unit custom autobanks for parallel testing. Interfaced with in-circuit testing (ICT) group to coordinate allocation of functional tests between functional test and ICT to maximize test coverage and throughput. Developed test applications in C/C++.Designed a multi-channel BERT tester to perform parallel bank testing of DDS, ISDN, and POTS products. More than $1M in test savings was realized during its first year of deployment. Design based around an Infineon C163 microcontroller, Maxim (Dallas) framers, and a Xilinx Virtex FPGA. Developed embedded C firmware using Keil µVision2. FPGA had multiple configurations, software selectable, for DDS, ISDN, and FT1 applications. Applied for patent in November 1999 (granted in 2003) to cover virtual BERT array technology.Mentored co-op engineers and guided them through their first board designs.

Arlington, Va, Us

Developed RS-170, digital video generator module for the Direct Support Electrical System Test Set (DSESTS) Horizontal Technology Integration (HTI) FLIR program. Implemented high-speed logic and state machines in Altera FLEX 8000 CPLDs.Designed multiple VMEbus cards for the Breacher Vehicle Electronics Subsystem. Designs included the system controller module and a sampling module for reading analog operator inputs. Responsible for boot code development and support of application development. Provided on-site vehicle integration support.Designed ISA bus card for use in the Army Contact Test Set--Electro-Optical Augmentation (CTS-EOA). Card performed 20 MSPS digitization of analog waveforms from the M1A2 Thermal Imaging System (TIS). Portions of the design implemented in Actel FPGAs.Lead engineer for the Design Tools Advisory Committee. Responsible for upgrading the engineering department to a new CAD system, including library reorganization and clean-up. Responsible for engineers and an engineering aide in support of this effort. Also involved in cross-departmental effort to integrate simulation and system design tools.

Ms, Engineering Management

Bs, Electrical Engineering