• Architect CAD system to unify design and layout methodologies across 7 design centers. • Implement verification methodologies to verify block, chip, multi-chip, and multi-chip plus PCB designs• Lead multi-site methodology team to create and implement common design, verification, layout, and documentation methodologies integrating best practices from all participants• Automate parasitic extraction flow to enable design engineers to get consistent results between runs and blocks reducing the potential of error when stitching blocks together for high level simulation• Perform extensive customization of foundry PDKs, including eliminating devices that were not to be used on a project due to mask or technology restrictions, customizing models to support wider range of PVT corners, customizing LVS decks to use deep trench isolation as a substrate dividing mechanism, and writing custom DRC rules to assist in debugging complicated DRC and LVS errors• Write data translation programs to translate netlists between multiple simulator and verification tool formats to enable porting of old designs to new technology and support for third party IP formats that were not compatible with Sequans design flow• Write custom SKILL to identify and modify CDF parameters of specific device values based on a table of default values • Write and maintained a simulation documentation collection tool to identify all important parts of a design and simulation in order to collate the information into a single object so that a simulation could be exactly reproduced in the future ensuring the exact design versions and testbench settings from the initial run• Create customization, automation, and training for 70 RF and digital design engineers across 7 sites• Liaise with corporate IT group to define and implement IT solutions based on engineering needs • Conduct multiple user training sessions based on self-created documentation of flows and methodologies

Define design methodologies for RF/Analog/Mixed-Signal design flowCreate automation of common layout tasks and layout verificationCreated design management system for sharing designs across 3 sitesWork with EDA tool vendors to evaluate and obtain EDA software

Physical Verification Engineer responsible for DRC, LVS and LPE with Mentor, Cadence, Synopsys, and Magma tools. Primarily focused on Calibre tools.