Verification of Radio FPGA | SystemVerilog, UVM, Questa Sim, Python Scripting➢ Coded an APDU Protocol Layer VIP to enable code re-use in 4 FPGAs. Coded an API to allow the VIP to be easily re-used with 2 agents. Created an isolated test to verify the APDU packet pack, unpack, and print functions.➢ Wrote random tests, prediction, and covergroups for 25 CCSDS transaction types, yielding 100% functional coverage.➢ Coded a protocol layer to enable SpaceWire transactions to be interpreted in CCSDS format. Wrote factory overrides to enable different formats for all 25 CCSDS message types. Integrated with the agent, sequence, and scoreboard.➢ Integrated SpaceWire read and write transactions with the UVM register model. Troubleshooted a write accesss issue.➢ Extended 3 sequences and wrote base tests to enable code-reuse among UART, SpaceWire, and APDU tests.➢ Troubleshooted a failing reset assertion, and diagnosed a bug in the testbench clock-multiplier Phase Locked Loop(PLL)Verification of Crypto FPGA | SystemVerilog, UVM, Questa Sim, Bash Scripting➢ Implemented a Bash script to automate README updates, enabling verification engineers to be 2\% more productive.➢ Troubleshooted 7 failing tests, communicated with designers to resolve 5 RTL bugs, and presented in a design review.➢ Coded an AXI bus width parameter, and updated the regressions to efficiently test 8, 16, and 32 bit configurations.➢ Updated the bidirectional data bus to be bi-state instead of tri-state, and adjusted assertions in the harness.

➢ Programmed in Python and LabVIEW to develop automated testing software for transistors➢ Coded and configured LAN communications to send SCPI commands between the PC and test equipment, reducing testing time by 10x➢ Created a GUI to allow the user to configure customizable tests, as well as Excel report generation➢ Coded automatic conversions between objects and XML formatting to save test settings➢ Coded test equipment synchronization to make test measurements at precise times, boosting test screening confidence by over 200%

➢ Performed mixed-signal verification and worst-case analysis on a 100V 1W Buck DC-DC converter. Wrote a Google Script to automate worst-case analysis and LTSpice circuit simulations. Improved efficiency by 5%.➢ Verified, designed, and tested a mixed-signal over-voltage protection circuit for DC/DC converters. Designed a 1mA memory latch that enabled reuse in 50 different DC/DC converters. Optimized the circuit for a cost reduction of 30%.

Verification of I2C Bus Controller ASIC | SystemVerilog, UVM, Questa Sim➢ Coded a UVM and SystemVerilog test bench to verify the functionality of an I2C bus controller. Defined coverage groups and bins to close in on 95% functional coverage using constrained-random and directed tests.➢ Wrote assertions to observe specific signal activity of the DUT. Performed simulations & debugging using Questa Sim.Design of Convolutional Neural Network ASIC | Verilog, Questa Sim➢ Designed, implemented and synthesized an area optimized neural network for image processing with varying size of input matrix. Implemented convolution, max-pooling and fully connected layers while interfacing with SRAM. Used parallelism & pipelining to optimize the number of cycles & clock frequency.DSP Kalman Filter | Matlab➢ Designed and implemented a DSP Kalman filter in Matlab to process 10hz lidar and 100hz accelerometer data for drone PID control.Team Lead of Drone Automation, Python➢ Led a team of 5 NC State Students to develop Python drone software for smokestack building inspections using Python.President of Company Outreach, IEEE➢ Co-led a team of 6 members responsible for planning 3 company Tech Talks at North Carolina State University.Web Development at scottfuntech.com➢ Coded PHP, SQL, and Javascript to implement a responsive hierarchical database, hosted on AWS➢ Derived and programmed a 3D image rendering algorithm using JavaScript and HTML