Scott Runner Email & Phone Number

Carlsbad, CA, US

Natcast is a purpose-built, non-profit entity created to operate the National Semiconductor Technology Center (NSTC), established by the CHIPS and Science Act of the U.S. government. The NSTC is a public-private consortium dedicated to semiconductor R&D in the United States. A key component of the CHIPS Act, the NSTC will convene the U.S. government.

Stealth-mode operation combining AI, semiconductor acceleration and open Software Defined Vehicles to create memorable and monetizable customer experiences. Stay tuned.

Mountain View, California, US

With an inspiring vision of "leveraging the Software-Defined Vehicle and "persona-driven use cases" to create memorable and monetizable experiences for VW brand consumers", transformed and united the hardware, platform OS, IVI and cloud teams to deliver CARIAD's 2.0 prototype products and demonstrate how car-to-cloud solutions can come together to break.

Paris, Île-de-France, FR

Lead a team of solution architects and over 3,000 embedded software engineers to solution with automotive and semiconductor clients in the co-creation of their most complex products including infotainment, ADAS/AD and telematics and V2X software, hardware and semiconductor chip designs. Further, identifying their future state objectives and driving.

Paris, France, FR

Lead the global embedded software and hardware practices for automotive, telco and semiconductor industries. Established an end-to-end chip and hardware development process for the most advanced chips down to 3nm including chiplet designs and state-of-art EDA tools and design and testing flows. Transformed the global organization from on focused mostly on.

Neuilly-sur-Seine, FR

Lead the integration of Aricent and Altran's 5G practices and the formation of the "Intelligent Industry" Car-to-Cloud offer which combined the best of onboard telematics, infotainment and ADAS systems with cloud capabilities in the realization of early 5G connected car use cases.

Santa Clara, CA, US

Driving the development and deployment of IoT, Automotive and Semiconductor Design Solutions to enable Aricent customers to quickly and reliably develop the most leading edge platforms at this pivotal point in the electronics industry.Aricent has capabilities in semiconductor design and embedded, communications, multi-media and cloud SW development.

San Diego, CA, US

Leading Qualcomm’s Automotive SoC Team for Infotainment, Telematics and ADASResponsible for automotive SoCs. Established Qualcomm’s automotive SoC design flow to deliver intrinsic silicon to support AEC-Q100 grade 3 SoCs, FPGA platforms and reference designs capable of supporting ISO26262 ASIL A – D levels. Included design, DV, DFT, PD, reliability.

San Diego, CA, US

Leading Low Power VLSI Design Identify, develop and deploy power/energy solutions which optimize power, performance along with area/AUC. Analyze energy expenditure per use case vs. customer requirements and competitive benchmarks to establish power targets and developed and deployed “Design to Power Budget” process to achieve such targets. Architect.

San Diego, CA, US

Led Qualcomm’s Design Verification, FPGA and Validation TeamsEstablished Qualcomm’s Design Verification flow and processes and led the verification effort for the world’s first mobile SoC with integrated Application Processor. Built DV team from scratch and company-wide verification (pre-silicon) & validation (post silicon) flow for all SoC products: MSMs.

Co-Founder, Processor DesignerEstablished engagements with Toyota, Olympus and Sony for a HW reconfigurable, low cost residential gateway device which networked content through 802.11, HomePlug, Ethernet, media storage for over-the-net HW upgrades. Toyota engagement was a model of early Bluetooth and Wi-Fi in-car WLAN.Engagement with ARM Ltd. involved.

Irvine, CA, US

Director of Central Engineering – ARM Cores & Subsystems, Standard Cells & Memory TechnologiesResponsible for ARM microprocessors & subsystems, including lead partner on the ARM946. Responsible for standard cell, memory and IO foundation libraries.

Irvine, CA, US

Director of Design Engineering - Network Access Devices Responsible for RTL to productization of Network Access Division development of various SoCs including framer/deframers, clock recovery and other similar designs. Included area, power and performance analysis, DFT, floorplanning, physical design, timing closure, test and product engineering. Also.

Sunnyvale, California, US

Relocated to Hillsboro, Oregon to integrate Logic Modeling and help open up Synopsys Oregon R&D center. Ran the engineering team for IP modeling and Virtual Platforms delivering VIP, HW-SW verification platforms and IP for microprocessor and peripheral IP.

Sunnyvale, California, US

Founding team of Synopsys DesignWare IP Reuse program – reusable, parameterizable design IP components linked to synthesis to enable faster, more productive, higher quality designs. Involved in several IP acqusitions.Also responsible for Synopsys Consulting Services and design methodology which enabled the industry to transition from schematic capture to.

1990 – 1992: ASIC Design Center DirectorRan all of Fujitsu’s North American design centers implementing customer ASIC designs in networking/elecomm, PC, mini computer and other market segments. Established first Synopsys synthesis-based commercial ASIC flow, and Fujitsu's IP Reuse program.1984 – 1990: ASIC Design EngineerSpecialized in DSP and ASIC design.

Bachelor Of Science (Bs), Applied Physics

Post Graduate Work, Computer Science & Engineering Management