Scott Runner Email & Phone Number

Carlsbad, Ca, Us

Natcast is a purpose-built, non-profit entity created to operate the National Semiconductor Technology Center (NSTC), established by the CHIPS and Science Act of the U.S. government. The NSTC is a public-private consortium dedicated to semiconductor R&D in the United States. A key component of the CHIPS Act, the NSTC will convene the U.S. government, allied and partner nations, and organizations across the semiconductor ecosystem—including academia and businesses of all kinds—to address the most challenging barriers to continued technological progress in the domestic semiconductor industry, including the need for a capable workforce. The NSTC reflects a once-in-a-generation opportunity for the U.S. to drive the pace of innovation, set standards, and re-establish global leadership in semiconductor design and manufacturing.The mission of the NSTC is to serve as the focal point for research and engineering throughout the semiconductor ecosystem, advancing and enabling disruptive innovation to provide U.S. leadership in the industries of the future.For more information on the stra

Stealth-mode operation combining AI, semiconductor acceleration and open Software Defined Vehicles to create memorable and monetizable customer experiences. Stay tuned.

Mountain View, California, Us

With an inspiring vision of "leveraging the Software-Defined Vehicle and "persona-driven use cases" to create memorable and monetizable experiences for VW brand consumers", transformed and united the hardware, platform OS, IVI and cloud teams to deliver CARIAD's 2.0 prototype products and demonstrate how car-to-cloud solutions can come together to break historic silos. Improved the speed and agility of development and enablement functions and created a team to support and the local brands to meet the unique needs of the US market.

Paris, Île-De-France, Fr

Lead a team of solution architects and over 3,000 embedded software engineers to solution with automotive and semiconductor clients in the co-creation of their most complex products including infotainment, ADAS/AD and telematics and V2X software, hardware and semiconductor chip designs. Further, identifying their future state objectives and driving transformation in the form of capabilities, processes and products. Lifecycle ranged from system engineering and architecture, to microarchitecture and modeling, to implementation and verification, validation and test. Also involved setting up the necessary methodologies and flows and partnering with tool and IP vendors to define, select and utilize the necessary IP and tools required to development and productize the product.

Paris, France, Fr

Lead the global embedded software and hardware practices for automotive, telco and semiconductor industries. Established an end-to-end chip and hardware development process for the most advanced chips down to 3nm including chiplet designs and state-of-art EDA tools and design and testing flows. Transformed the global organization from on focused mostly on staff augmentation, to that focused on spec-to-silicon VLSI design.

Neuilly-Sur-Seine, Fr

Lead the integration of Aricent and Altran's 5G practices and the formation of the "Intelligent Industry" Car-to-Cloud offer which combined the best of onboard telematics, infotainment and ADAS systems with cloud capabilities in the realization of early 5G connected car use cases.

Santa Clara, Ca, Us

Driving the development and deployment of IoT, Automotive and Semiconductor Design Solutions to enable Aricent customers to quickly and reliably develop the most leading edge platforms at this pivotal point in the electronics industry.Aricent has capabilities in semiconductor design and embedded , communications, multi-media and cloud SW development, verification and validation and has developed commercial solutions for various IoT applications such as wearables, SmartSpaces, SmartEnergy, automotive designs in the connected car and infotainment space, and SoC designs down to the 10nm geometry.Led the planning and execution of Automotive V2X based SoCs and FPGA platforms, IoT devices for SmartCity, SmartHome and Wearables (VLSI, HW & SW), including pre and post silicon activities.

San Diego, Ca, Us

Leading Qualcomm’s Automotive SoC Team for Infotainment, Telematics and ADASResponsible for automotive SoCs. Established Qualcomm’s automotive SoC design flow to deliver intrinsic silicon to support AEC-Q100 grade 3 SoCs, FPGA platforms and reference designs capable of supporting ISO26262 ASIL A – D levels. Included design, DV, DFT, PD, reliability, analog, PTE and Quality & Reliability aspects. Successfully delivered Qualcomm’s first SoC AEC-Q100 grade 3 device, as well as several telematics devices. Involved in architecture of next generation ADAS FFC and infotainment devices. Worked with tier 1s and OEMs to understand SoC requirements and discuss and present design, quality and reliability solutions.

San Diego, Ca, Us

Leading Low Power VLSI Design Identify, develop and deploy power/energy solutions which optimize power, performance along with area/AUC. Analyze energy expenditure per use case vs. customer requirements and competitive benchmarks to establish power targets and developed and deployed “Design to Power Budget” process to achieve such targets. Architect, develop and productize next generation power management solutions from cradle to grave. Work across all worldwide IP and SoC teams to ensure power roadmaps established and “design to power budget process” to satisfy. Established “PPA” flow to identify most efficient workload-driven operating points resulting in 15-20% power improvements and 3-7% area improvements. Developed thermal and current limits management hardware, HW DVFS and boost circuits which optimize SoC power & performance. Lowered ARM licensed (A57, A72, A53) CPU power by 60% in less than 1 year. Drove mixed signal verification for analog sensor validation resulting in first time mixed signal design operation.

San Diego, Ca, Us

Led Qualcomm’s Design Verification, FPGA and Validation TeamsEstablished Qualcomm’s Design Verification flow and processes and led the verification effort for the world’s first mobile SoC with integrated Application Processor. Built DV team from scratch and company-wide verification (pre-silicon) & validation (post silicon) flow for all SoC products: MSMs, MDM, APQs, MPQs and enabled PMIC and RF/WTR verification and quality improvements. Reduced the number of respins to reach production from 8-12 to 1.1 and enabled first time success of Qualcomm’s most complex SoC. On the leadership team that established Qualcomm’s Bangalore Design Center via acquisition and integration team of Spike Technologies. Managed pre-silicon FPGA platform and validation teams and post silicon validation team. Supported baseband and RF pre-silcion FPGA emulation and brought up platforms for Veloce and Palladium Simulation Acceleration to complement FPGA based platforms.

Co-Founder, Processor DesignerEstablished engagements with Toyota, Olympus and Sony for a HW reconfigurable, low cost residential gateway device which networked content through 802.11, HomePlug, Ethernet, media storage for over-the-net HW upgrades. Toyota engagement was a model of early Bluetooth and Wi-Fi in-car WLAN.Engagement with ARM Ltd. involved studies and architectural designs of programmable phy layer solutions for networking which contributed to what became ARM’s M-class architecture.

Irvine, Ca, Us

Director of Central Engineering – ARM Cores & Subsystems, Standard Cells & Memory TechnologiesResponsible for ARM microprocessors & subsystems, including lead partner on the ARM946. Responsible for standard cell, memory and IO foundation libraries.

Irvine, Ca, Us

Director of Design Engineering - Network Access Devices Responsible for RTL to productization of Network Access Division development of various SoCs including framer/deframers, clock recovery and other similar designs. Included area, power and performance analysis, DFT, floorplanning, physical design, timing closure, test and product engineering. Also responsible for EDA tools, end to end design flow.

Sunnyvale, California, Us

Relocated to Hillsboro, Oregon to integrate Logic Modeling and help open up Synopsys Oregon R&D center. Ran the engineering team for IP modeling and Virtual Platforms delivering VIP, HW-SW verification platforms and IP for microprocessor and peripheral IP.

Sunnyvale, California, Us

Founding team of Synopsys DesignWare IP Reuse program – reusable, parameterizable design IP components linked to synthesis to enable faster, more productive, higher quality designs. Involved in several IP acqusitions.Also responsible for Synopsys Consulting Services and design methodology which enabled the industry to transition from schematic capture to RTL synthesis. Created rotation program between consulting and IP development.

1990 – 1992: ASIC Design Center DirectorRan all of Fujitsu’s North American design centers implementing customer ASIC designs in networking/elecomm, PC, mini computer and other market segments. Established first Synopsys synthesis-based commercial ASIC flow, and Fujitsu's IP Reuse program.1984 – 1990: ASIC Design EngineerSpecialized in DSP and ASIC design from spec to GDS and post silicon support

Bachelor Of Science (Bs), Applied Physics

Post Graduate Work, Computer Science & Engineering Management