Scott Wincklhofer Email & Phone Number

Florham Park, Nj

Murray Hill, Nj

Built a team from the ground up to a peak of 30 engineers doing LTE Modem Layer 1/Layer 2 development in 'C' on the ALU BCEM platform (Freescale P4080). The initial team was staffed with developers from the UMTS product so there was a significant learning curve for the team to overcome with my support. Subsequent features were staffed in a similar manner as older technologies downsized. I was able to create a supportive environment which allowed the team to ramp their knowledge while still delivering on commitments. The team utilized Agile practices and were divided into 3 separate SCRUM teams. I played the Product Owner role for each. Following SCRUM principles the teams were cross functional including modem development and system test. The teams were also geographically diverse utilizing test teams in Europe. Source code was strictly controlled under Clearcase and change management tracked in DCT. Over this time period several critical features were delivered with high quality. 15 Mhz Bandwidth SupportGeneralized Over Provisioned PUCCH Non GBR QOS Differentiation MCS/PRB OverrideRACH Format 2Category 4 UE SupportConvergence of TDD and FDD codebaseInterference Rejection Combining4x2 DL MIMO SupportI was Feature Owner for each of the listed features. Planned and drove the feature development across the entire system from concept through GA in the customer's network. Coordinated the interactions across multiple development and test domains. Tracked progress, managed risk and resolved bottlenecks providing regular updates to the stakeholders. Supported the initial customer roll-out of the features.

Murray Hill, Nj

LTE Layer 1 Uplink FPGA (2007 - Present)Built a team of developers who designed and maintain a Layer 1 LTE Uplink Modem device targeted to a Xilinx XC6VLX365 device. The team spearheaded ALUs LTE development, producing the demonstration systems that were critical in ALUs early LTE contract success in the U.S. The device has since been ported across three generations of ALU modems containing successive Xilinx FPGA families (Virtex 4 - Virtex 6). New features are added to the device with each release to support the overall ALU roadmap. The team follows a strict ASIC like development process in VHDL, stressing simulation, and prides itself on it's “first time right” success record. UMTS Layer 1 HSDPA FPGA (2004-2014)Managed a team of 11 developers designing an HSDPA physical layer device. The device is targeted at a Xilinx LX60 FPGA. The team followed a disciplined ASIC/FPGA design processes throughout the development, resulting in very few errors being detected during board level integration. The design is currently being enhanced to support UMTS Release 6 features.Authored the original draft of the Lucent Mobility Systems ASIC/FPGA design process. This is a full cycle development process encompassing Algorithm development through device verification. I worked with a cross functional team to complete the process and incorporate CMMI Level 3 compliance.

EVDV Rev C Device(2002-2004)Managed a team of ASIC developers designing a EVDV Rev. C physical layer device including intelligent antenna functionality. This team included 24 members in multiple locations. My primary responsibility was to manage the team and the ASIC development schedule. This included the refinement of our standard ASIC process to reduce the previous development interval by 6 months. I also retained final decision on all major technical issues. The device has 10 million gates and 20 Mbits of memory operating at 160 Mhz. The device features an ARM 10 core and standard PCI interface. The device is being fabricated in a .13m process.CDMA 2000 (3G1X) device (1999-2002)Managed the development of a 3G1X physical layer device. This team includes 26 members in multiple locations, including India. I was responsible for managing the team and the overall ASIC project schedule. This included the development of a standard ASIC process that streamlined the interactions of the team members. I also retained final approval on all major technical decisions. The device has 4 million gates running at 160 Mhz in a .16m process. The device is signal processing intensive, but uses no standard cores. The device was a first pass success. IS-95 A/B device (1998-1999)I managed the development of a cdmaOne (IS95) physical layer device. The device has .5 million gates running at 20 Mhz in a .25um process. I assumed responsibility for this team in the middle of the implementation phase. I lead the team of 15 engineers through verification and fabrication phases. The device was a first pass success.

Architect Wireless Forward Looking Team DDI/IDO 3G3x prototypeI was the lead engineer on proposal team responding to a next generation cdmaOne (IS-95) RFP for DDI/IDO in Japan. The proposal was successful and lead to a multi-year prototyping contract.Docomo WCDMA (UMTS) prototypeI was the lead engineer in effort to architect a prototype Wideband CDMA system for NTT Docomo. I was responsible for the overall hardware partitioning in the prototype basestation. The prototype was delivered to DoCoMo and did secure a development contract for Lucent. Flxent BasestationI was a lead hardware engineer in effort to architect Lucent's Flexent Cellular Basestation Product. This architecture formed the basis of a very successful line of Lucent eNodeB products.Board Designer Wireless Forward Looking Team 3G3X prototypeI was a member of a team which, designed and demonstrated CDMA 2000 3x Cellular Basestation. I was directly responsible for the development of the DSP subsystem based upon two TI 320C54x digital signal processors. The system was used to successfully demonstrate high speed data transfer at CTIA.Block Radio demonstrationI designed and demonstrated a baseband processing board for a software radio prototype system. I was responsible for the complete board design including a Lucent 1610 DSP subsystem and two Xilinx 4000 series FPGAs. The system was successfully demonstrated to several key customers.ASIC Designer Federal SystemsHobbit MicroprocessorI designed LCD controller for microprocessor support ASIC and coordinated the design and synthesis of a three ASIC microprocessor chipset. These devices were designed to support the AT&T Hobbit microprocessor in pen based computing applications. SEM E EMSP Digital Signal ProcessorI designed, simulated, and verified a CMOS VLSI data interface ASIC for the EMSP SEM-E digital signal processing system. The design was a first pass success. I held a Secret clearance for the duration of this project.

Masters, Electrical Engineering

Activities and Societies: Tau Beta Pi, Eta Kappa Nu

Bachelor Of Engineering, Electrical Engineering

Activities and Societies: Tau Beta Pi