gCPU DV

1. ARM v9a CPU IP co-DV Lead: 2022Q4 I lead ~40 DV engineers in our customer (ARM China) and Anshingtek separated into 10 DV Units: 1 top, 2 multi-unit, 6 units (fully based on UVM) and formal verification (include ISA-Formal) from initial investigation to end of ALP. (passed ALP review) 2. Anshingtek co-Engineer Manager (manage 20+ engineers) - host Anshingtek Monthly all-hands since 2022-Jan.3. I built an in-house tool to create ARMv9a architectural model by interpreting the up-to-date ARMv9a pseudo code (such as 2022-06) and successfully deployed it to uArch Performance Model, Core Pipeline DV, MMU DV and ISA-Formal. The tool is based on the technologies includes ASL, OCaml, Python, A64/A32 assembly, C and SystemVerilog.

CPU/AI DV Project Operation: (lead 28 people)1. Single Core (in-house RISC-V) CPU DV: fetch, decode, branch predict, multi-issue/thread, forward, interrupt, debug, PMU, cache/TCM, FPU, vector extension.2. Cache Coherency Interconnect and shared L2/L3 Unit DV. (in house coherence interconnect for ARM v8.0 CPU)3. Integrated CPU System DV (ARM v8a/v9a licensed IP): SMP/HMP Multiple Core System functional, performance and power. (based on portable stimulus)4. AI (in-house DLA): fixed/float variable bit width data type conversion, convolution, activation operations, weights/feature maps Compression, flow controller.Verification Methodologies:Formal (app, sign-off or bug hunting), Portable Stimulus (multiple C, SV scenarios), UVM (layered stimulus)

1. CRV: UVM/SV Execution, Deployment and Methodology. (Bus Interconnect, Ethernet Switch...) 2. Emulator Technology (Palladium, Zebu, Veloce): Execution, Deployment and Methodology3. Power Aware (UPF) flow establish, Formal/SVA, CDC, Lint, h/w-s/w (tarmac) debug supports.4. In-house DV Related AIP/VIP and Utilities (coverage, regression, permission management)5. Resource Management: people, licenses, LSF queue (machine slots).

1. Help to build a UVM supporting team to deliver training, consulting, methodology migration co-work(service) and guild many DV teams to setup their DV framework and solve daily verification challenges.2. In charge of H/W accelerators flow. (succsessfully deploy Palladium to modem team)

Verification Methodologist1. In charge of USB30 DV (2 DUT: xHCI Host and proprietray device): hands-on and finish the 1st project (~180 RTL bugs fixed in 10 months & make FPGA/Silicon MP smoothly) & then transfer to others.2. Deliver UVM training (to bring up DV engineers) and provide consulting during execution.3. Attend to DVCon 2012 and read all 2010-2011 DVCon Papers.

1. Verification Methodologist (self study OVM) 2. Coaching 3 members to verify with OVM: verifying USB20 Device and NAND Flush Controller.

1. USB10/20 Host Controllers Design from scratch. (RTL coding, direct test and FPGA prototyping, post-silicon validation and customer engagement especially when they attached new type of device into our solution) - 2 flavors of design 1 follows OHCI/EHCI another is proprietary design which supports both roles(host and device)2. licensed IEEE1394 Controller IP maintenance.3. Help to build a 14 people design/verification team in ChengDu at 2006. (they grew to 37 people in 2009) // include recruiting/training/goal setting/tracking/review