Sean Sam Email and Phone Number

•Managed a team of PD engineers and drove functional/test mode timing closure for persistent memory, IPs/Clusters on 5G base station SoC. •Collaborated with RTL, IP, cross functional, cross-site PD team with timing reviews session, timing constraints management with PPA focus.•Communicated to management on tape-in schedule and risk mitigation, setting priorities for the team to get results across cross functional areas.

•5G Base station product for external customer defined PVTs corner, timing modes and clock/exception reviews with customer. •Block execution pushed through synthesis/PNR stages, ECO’s at Intel Custom Foundry, implemented high/slow clock trunk distribution and testchip convergence.•Second generation micro-server product drove sub-fullchip timing convergence effort worked with multiple Hard/Soft IP cross site teams.

•Tool evaluation worked with Synopsys AE to enhance ICCDP feature (pin cutting, feedthru mapping, pin alignment). •First generation micro-server product responsible for fullchip floorplan created multiple floorplan options meeting architectural and RTL requirements. •Modular floorplan and hybrid methodology to create logical/physical partition, pushdown powergrid and signals pins to partitions using synopsys/cadence tool.

•Partition execution owner for PCIGen3 transaction layer on server chipset performed all aspect synthesis, macro placement, PNR, drc/lvs/functional eco for block signoff.•Responsible for global/local clock tree implementation for processor IO subsystem, performed clock simulation, managed cts specs and implementation.•Clock Tree Synthesis for server chipset maintained clock tree flow, defined insertion delay spec and skew requirement for multiple drop-of point methodology.

Developed functional test plans & cases for memory controllers (DDR & Flash). Generated vectors to verify functionality of DDR SDRAM, Burst (PSRAM & NOR flash) memory controllers & running functional simulations.