Sean Sequeira Email & Phone Number

Bengaluru, Karnataka, India

Part of CEG (Client Engineering Group) DDRPHY IP team. Operating as senior manager and Bangalore site lead for the DDR PHY IP team leading Front End Design, Verification & Firmware teams of 40+ engineers. Responsible for flawless execution of front-end aspects of DDR PHY IP (Design, Verification and Firmware) to ensure timely, high quality delivery of cutting edge, next generation DDR PHY IPs to the Memory Controller Sub-System and SOC

Bengaluru, Karnataka, India

Part of IPSE (IP Solutions Engineering) team in PSG (Programmable Solutions Group), Intel. Operated as senior manager for team of 25+ engineers, with the charter being Functional verification of DMA Controllers, Reset Controllers and Ethernet IPs, delivered on time and with high quality to external customers through QPDS (Quartus Prime Design Software). Worked as IP owner for Ethernet IPs, leading design & verification teams to deliver IPs meeting schedule and quality requirements. Served as single point of contact (SPOC) while managing/leading a team of design & verification engineers delivering IPs from Bangalore site into multiple critical PSG projects

Bengaluru, Karnataka, India

Part of MIG (Mixed-Signal IP Solutions Group) Verification team. Operated as senior manager for the DDR PHY verification team of 15+ engineers, with the charter being Functional and DFx verification of DDR PHY, delivered on time and with high quality to the Memory Controller Sub-System and SOC

Bengaluru, Karnataka, India

Had a brief stint in CIG (Chipsets and IP Technologies Group) Verification team, where I worked on SCS (Storage and Communication Sub-System) and LPSS (Low Power Sub-System), and was responsible for subIP integration (RTL and Verif collaterals) and bring-up, functional coverage plan definition and implementation leading a team of 2 engineers, contractor task assignment, tracking, mentoring, IP/SOC engagement, bug tracking

Bangalore

Part of MCU32 (32 bit microcontrollers) IP Verification team. Operated as Verification Lead, and was responsible for verification of digital IPs like Cache controller, Memory controller, 10/100Mbps Ethernet MAC, SD2.0 Host Controller, using SV-VMM testbench, identifying and porting appropriate tests from IP level to SOC level for integration verification, defining QADMS based mixed-signal verification flow at IP level, enhancements to existing flow to improve RTL and TB check-in quality, setting up cron based daily regression runs to report pass-rate, functional and code coverage numbers for transparent tracking of verification progress on a daily basis. Briefly responsible for UPF based power-aware RTL simulations at SOC level. Participated in Microchip Verification Council meetings where flow and methodology related items are discussed and rolled out.

Verification lead and owner for macros like PLLs, Voltage regulator, Clock stretcher, voltage monitors. Also responsible for tools and methodology for mixed-signal IPs. Involved in functional verification of MIPIDSI PHY.

Responsible for verification of PLLs. Pioneered PLL verification at AMD, India and helped grow the team to own verification of almost all PLLs at AMD.

Responsible for mixed-signal integration and verification of SERDES and IO characterization. Pioneered mixed-signal integration and verification at PMC Sierra, India. Ramped up quickly and helped build the team in India (full-time engineers and service providers) to take up complete ownership and execute projects independently.

Responsible for various things: SOC level verification, IP level verification, STA, Synthesis, ECO scripts, RTL coding, SPICE simulations of first generation on-chip VREG, behavioral modeling. Proposed and defined Nanosim-VCSMX based mixed-signal simulation flow for TI-AEC (Advanced Embedded Controllers) SOCs.

Responsible for phone support of Dell desktops.