- 20+ years of experience in VLSI design/verification during which I worked in digital, analog and mixed-signal domains- Functioning as manager/leader for IP design/verification/firmware teams of 40+ engineers (full-time and contractors)- Experienced in people management, vendor management, hiring, detailed project planning & tracking with focus on high quality, flawless execution- Worked with cross-geo, cross-functional teams, and mentored team on handling challenges effectively- Experienced in taking up pilot projects, setting up teams from scratch, and instilling a collaborative, high performing & result-oriented culture- Handled complex ASIC/FPGA IPs like Memory Hard IPs, Memory controllers, Ethernet IPs,... and worked in IP, Sub-system and SOC levels- Exposed to behavioral modeling, IO characterization and generation of .lib files- Exposed to STA, Synthesis, writing ECO and PERL scripts, Equivalence checking, RTL coding in VHDL & Verilog, Linting, and verification using ARM assembly- Experienced in Synopsys, Mentor Graphics and Cadence (limited exposure) based mixed-signal co-simulation flows for functional verification- Expertise in various aspects of logic/functional verification like DTP (detailed test plan) creation including testbench architecture definition, RTL/Gate/Power-aware verification, SPICE or Verilog-AMS based mixed-signal verification, Coverage, Regressions, Debug- Experienced in VHDL, Verilog and System Verilog (UVM/VMM) based verification environment- Experienced in defining customer-centric flows like Nanosim-VCSMX based mixed-signal verification flow for TI-Advanced Embedded Control (TI-AEC) group- Exposed to correlating silicon data to simulations using mixed-signal co-simulation flow