Responsible for the physical implementation of Video Codec Hard Macros for Exynos low power processors and ModAP (application processor including a modem) in 28nm and 14nm.Co-lead an initiative on innovation in Samsung France Research Center.

Lead the design of an OMAP5 SoC derivative.

Responsible for the physical implementation and tape-out of OMAP5430/32.Project Management:• Drove design team activities from netlist to tape-out. (Team of 17 engineers + some subcontractors.)• Defined work breakdown structure, deliverables and milestones.• Developed and maintain top-level schedule. Assess resources needs. • Worked with multi-site and multi-cultural teams. Defined and negotiated deliverables, milestones and quality requirements with Indian, American and local teams.• Managed technical risks. Lead peer reviews and lessons learned.• Worked with external EDA vendors to get releases of the tools which would be able to handle OMAP5 complexity.• Ensured compliance to TI quality process and standards.• Communicated effective team activities reports at several hierarchical level of the company.• Co-lead a cross-functional multi-site 28nm Task Force during 7 months: Defined priorities, reviewed technical risks and presented the results to senior management in two worldwide reviews. Technical aspects:• TI’s first integrated circuit in 28nm process: low-power multi-million gates design including a dual A15 ARM core, multiple voltages and power domains, complex clock trees, static and dynamic power management. Able to support LPDDR2 or DDR3 in two different packages.• Team’s responsibility : design work from Netlist to GDSII (Synthesis - STA - Place and route - Timing and leakage optimization – Static and dynamic IR drop analysis - Physical design checks – Tape-out).• Handled new constraints introduced by the 28nm process.

Responsible for the entire development of a complex custom SoC for wireless applications.Project Management:• Drove design activities from specification to production. (Team of 30 engineers).• Interface to customer on technical aspects and project status, supporting multiple weekly meetings.• Executed and maintained project management processes in the areas of: project schedule, resource level assessment, risk management, bug tracking and change management, statement of work (SOW) definition, TI quality standards compliance.• Provided bi-weekly project progress updates to senior management of both companies.Technical aspects:• Custom SoC integrating a 65nm process modem die stacked on an application processor die, both sharing a POP (Package on Package) RAM.

In charge of physical design activities for custom Ericsson SoCs and hard macros in 130, 90 and 65nm.Team management:• Secured 90nm parallel designs execution by defining standardized flow and methodology and by organizing best practices sharing, lessons learned and regular technical working sessions.• Led the TI team during the execution of a 65nm SoC, working closely with Ericsson STA team to ensure permanent alignment between teams.• Managed yearly reviews of team members (5 engineers).Technical aspects:• Responsible of defining physical requirements for megacells deliveries from TI India teams.• Drove the integration of timing closure team in the physical design team to support 65nm challenges.• Defined the 65nm custom timing closure flow and deploy it on customer side through trainings.Achievements• The team made 4 successful tape-outs during this period (1 in 130nm, 3 in 90nm)

Responsible for the migration of a custom digital baseband SoC from 0.18um to 0.13um process.Project Management:• Handled customer communication and support, TI quality process, test engineers, QA and package teams’ interface during design, characterization and qualification phases.Technical aspects:• Defined project plan and working methodology for all design tasks (RTL updates, specific synthesis approach, DSP hard macro update, gate level simulations debug, documentation).

Performed and supported TI customer on various design tasks for 180nm and 130nm ASICs: RTL integration, synthesis, verification, clock & reset design, CTS, DFT, soft IPs and memories choices, DB management, TI flow deployment.

Worked on Design For Test aspects for several soft IP modules in 0.25um and 0.18um.

Worked on a test chip in 0.25um process.(RTL, synthesis, IO ring definition, floorplanning)

Worked on optoelectronic and microwave devices dedicated to defense electronics countermeasures and radar systems.