See Fee Wong

See Fee Wong Email and Phone Number

Program Manager at Intel Corporation @ Intel Corporation
santa clara, california, united states
See Fee Wong's Location
Penang, Malaysia, Malaysia
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About See Fee Wong

Experienced R&D Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Communication, EDA, Microprocessors, Application-Specific Integrated Circuits (ASIC), and Semiconductors. Strong arts and design professional with a Bachelor's Degree; Bachelor of Information Technology (Hons) focused in Computer Science/Information Technology from Institute/University : Multimedia University (MMU).

See Fee Wong's Current Company Details
Intel Corporation

Intel Corporation

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Program Manager at Intel Corporation
santa clara, california, united states
Website:
intel.com
Employees:
133841
See Fee Wong Work Experience Details
  • Intel Corporation
    Project Manager
    Intel Corporation Nov 2020 - Present
    Penang, Malaysia
    Drive and manage overall recourses and schedule for all flag ship program from Path-finding till design execution tape out in Programmable Technology & System Engineering team.Owned overall PTSE PLC and resources management from Product definition till Product rollout. To ensure each milestones fulfill product quality and schedule as per POR. Owned Program Management dashboard with monthly pulse check with OKR fulfilled. Manage and drive overall PTSE technologies readiness communication management i. PPE Perforce Owner for CTSE Collateral managementii. HSD ticket structure & process management iii. PTSE Infra & Storage managementiv. Share point & TEAM management
  • Intel Corporation
    Packaging R&D Engineer
    Intel Corporation Dec 2015 - Present
    Penang, Malaysia
    Job expansion from design automation to design infra setup, environment setup, design flow integration plan from planning to tape out for PTSE team include both Electrical and design team. Drive Intel infra (Include Hardware, computation requirement, storage requirement, tools, licenses and design environment setup) support to ensure smooth Intel integration process from Penang for New and Legacy products.Drive overall Intel xpedition package design flow - Overall package design flow with tools readinessDefine & evaluate Project Time, Cost which include resource, training, tools and hardware. Define project schedule, success criteria, required tools, prioritize, project cost estimated and risks. Identify needs and develop wrappers to link different tools and methodologies in design flow for New Product Rollout.For Legacy Product support•Develop internal custom automation to support legacy project, second source and automotive project•Develop 100% automation tools to improve for process efficiency, productivity, and quality of work.•Ensure hardware, software and design environment compliance in Intel process for all legacy projects - Key Person to coordinate tool implementation and testing between US SJ and Penang. Involve setting up CAD tools, flow and license management- Responsible for CAD tools and methodology application support. Improve the design flow, methodology, efficiency by evaluating solutions from external vendors or develop it internally. . - Experience with Cadence Allegro SKILL, IC-Packaging Co-design EDA tool, VFP and Digital SIP Layout, Orbit IO bump planning, Mentor XPCB, Mentor XPI
  • Altera Corporation
    Ic Packaging Engineer
    Altera Corporation Dec 2007 - Dec 2015
    Specialization : Engineering - Electronics/Communication Role : CAD-CAM/Electronics Drafter Industry : Semiconductor/Wafer Fabrication Work Description : - Responsible for CAD tools and methodology application support. Improve the design flow, methodology, efficiency by evaluating solutions from external vendors or develop it internally. - Key Person to coordinate tool implementation and testing between US SJ and Penang. Involve setting up CAD tools and license management- Support advanced package design environment setup and automation, design data management & tools management, design verification and automation - Work closely with cross-functional team and involve in co-design process engineering flow, planning, evaluating, implementation, testing and debugging- Develop and support advanced design development checking, design kit and environment setup to fulfill Manufacturing requirement and verification from die level to BGA Ball. - Experience with Cadence Allegro SKILL, IC-Packaging Co-design EDA tool, VFP and Digital SIP Layout, Orbit IO bump planning, Mentor XPCB, Mentor XPI- Support and ensure hardware, software and design environment compliance in Intel process for all legacy projects- Possess content management / development skills in the following:Visual Basic programming for MSOffice documentation automationMicrosoft SharepointVersion controlled software Perforce and IC Manage
  • Motorola Penang
    Software Enginner (Junior Executive)
    Motorola Penang Dec 2005 - Dec 2007
    Specialization : Engineering - Electronics/Communication Role : R&D Engineer Industry : Telecommunication Work Description : - working in a team to design, develop and execute tests to ensure our two-way radio software operates perfectly.The products being tested are two-way radios (walkie-talkies) and have extensive software content. - experience writing test plans, managing test personnel and equipment, reporting test status and summarizing test results - Learn advance data communications skill. Understand the different type of signal frequency such as UHF, VHF etc., sampling technique, digital modulation technique and encoding & decoding technique. - Learn advance RF communication protocol & Truncking system skills & knowledge. Understand the different type of RF communication conventional feature such as MDC/QCII/DTMF and truncking system such as SmartNet, SmartZone & etc - Learn and exposed used radios or it's infrastructure setup in either developing, maintaining or using it in the context of hardware or software for more than a year but less than 2 years. Able to apply the communication signaling knowledge in identifying most of the problems on communication signaling and able to fix some the problem if it's within scope
  • Motorola Cyberjaya
    Software Enginner (Junior Executive)
    Motorola Cyberjaya Jun 2005 - Nov 2005
    Specialization : Engineering - Electronics/Communication Role : Industry : Telecommunication Monthly Salary : MYR 2700 Work Description : - Develop and test telecom software application on Unix and NT - Responsible for the requirements analysis, design, implementation and unit test ofsoftware modules - Work with various teams to test target software releases and resolve software issues - Develop and execute test plans, scripts and test simulators - Adhere to the process defined for undertaken project and provide required metries datafor these activites - Support and maintain of delivered software
  • Interwerk-Systems
    Intern
    Interwerk-Systems Mar 2004 - Jun 2004
    Specialization : IT/Computer - Software

See Fee Wong Skills

Debugging Semiconductors Asic Testing Ic Microprocessors Cadence Integrated Circuit Design Fpga Eda C++ Open Minded Quick Thinker Communication Skills Perl Linux Red Hat System Administration Cross Functional Team Leadership Unix

See Fee Wong Education Details

Frequently Asked Questions about See Fee Wong

What company does See Fee Wong work for?

See Fee Wong works for Intel Corporation

What is See Fee Wong's role at the current company?

See Fee Wong's current role is Program Manager at Intel Corporation.

What is See Fee Wong's email address?

See Fee Wong's email address is ws****@****hoo.com

What is See Fee Wong's direct phone number?

See Fee Wong's direct phone number is (408)-544*****

What schools did See Fee Wong attend?

See Fee Wong attended Universiti Multimedia Selangor, Institute/university : Multimedia University (Mmu).

What skills is See Fee Wong known for?

See Fee Wong has skills like Debugging, Semiconductors, Asic, Testing, Ic, Microprocessors, Cadence, Integrated Circuit Design, Fpga, Eda, C++, Open Minded.

Who are See Fee Wong's colleagues?

See Fee Wong's colleagues are Daniel Schmidt, Helen Liu, Joel Leone, Daniel Mastarone, 张聪聪, Kailun Qin, Graeme Maher.

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