•Building a low power CPU core featuring a disaggregated module architecture, across diverse process nodes.•Writing tcl and python scripts to help automate and implement PTECOs to address timing, IR, data RC delay issues to meet critical path requirements in response to silicon feedback, PDK modifications.•Analyzing primetime reports to address setup and hold timing violations across all timing corners

• Working with the backend structural design team to understand, debug and implement the power intent (UPF, IEEE 1801) specification, to facilitate the power planning of a high frequency, very-low power CPU design by applying low power design techniques.• Using RTL to GDSII flow optimization tools to place macros and standard cells and realize power and chip area utilization results along with assessing the post placement QoR and timing reports for any violations and coming up with ways to fix them. Writing python scripts for manipulation, analysis, and extraction of this data.• Generating and understanding integrated circuit mask layout data files for base layer and metal layer fill.

Working on a thesis towards completion of Masters degree at Texas A&M University