Successfully completed high precision 12 bit 5 Msps SAR ADC in C40LP. It has asynchronous architecture, is ultra low power (520uA), wide supply swing 1.6V to 3.6V.My current responsibilities are:Responsible for feasibility, design, development and verification of ADC/DAC, ensuring its successful integration in SOC, with target of FTSS (first time silicon success). Detailed activities include:• Capturing and analyzing design specifications (resolution, speed, DNL, INL, offset, gain error, SNR, THD, power, area, technology) and defining architecture to meet specification. • Performing feasibility analysis of specifications and architecture, identifying opportunities for innovation, power reduction, and area reduction. Taking approval from customer for specifications, schedule and cost.• Defining blocks required for architecture implementation and calculating block specifications from top level specifications. For instance o Noise Calculationso Gain, BW, feedback loop analysis of opampo Gain-BW of comparator o Bandgap based reference voltages and currentso Delay and zero failure of level shiftero RC settling and clocking of switched capacitor circuitso Full custom digital logic• Designing circuit schematic and conducting simulations to measure performance against specifications, across PVT variations. Debugging for specification failure and fixing design issues.• Designing full custom layout of critical blocks, including block level, top level and also floor planning. Driving a team of layout designers for designing efficient layout and ensuring procedures to minimize impact of layout effects, including DFM, latch-up prevention, ESD protections, electro-migration rules, IR analysis, device matching, differential symmetry, shielding of sensitive nets, proximity effects, substrate isolation, low parasitic, etc.• Performing layout extraction and post layout simulations. • Supporting SOC team, for integration. Testchip design and silicon validation.

Some important projects done in ST tenure are:1) Low power, high precision SAR ADCs- 2.4mW/8bit/20Msps, area 0.08 mm2 for low energy bluetooth- 2.8mW/14bit/250Ksps, area 0.15 mm2 for ADAS- 1.3mW/10bit/1Msps, area 0.06 mm2 for NFC- 0.6mW/8bit/10Msps, area 0.05 mm2 as RSSI- assisted in verification of 16bit/4Msps for general purpose high performance microcontroller2) Low power, high resolution sigma delta audio DAC reconstruction filter.- 10mW/100dB-SNR/20bit, area 0.15mm2 for set top box- 1.3mW/97dB-SNR/24 bit, area 0.07mm2 - 8mW/101dB-SNR/24 bit, area 0.35 mm2 for Car Entertainment System- 1.2mW/80dB-SNR/14 bit, area 0.16mm2 for FM radioThese projects were developed in multiple technologies including 0.18u/0.13u/90nm/65nm/40nm/32nm/28nm Bulk/28nm UTB-FDSOI and achieved FTSS.