Co-Lecturer:- VLSI Design II: Basics of computer architecture, ASIC design flow and Cadence Virtuoso tools including Genus and Innovus. Designing a RISC-V based RV32I ISA core, performing synthesis, PnR and signoff by using TSMC90 and XFAB processes.- Digital System Design and Applications: Verilog HDL, FPGA design flow and Xilinx Vivado. Designing basic computer arithmetic and image processing circuits, block designs with Xilinx IPs, realization of the designs by Xilinx FPGA boards.Assisted Courses:- Data Structures and Programming- Intr. to Embedded Systems- Digital Filters&Systems- Logic Design Laboratory- Intr. to Electronics Laboratory

Co-lecturer at Summer Internship Programme: Basics of VHDL and FPGA design flow with Xilinx Vivado. Microblaze based designs by Vitis IDE.

- Layer 2 software development for LTE Base Station.