Xujia(Serena) Liu Email & Phone Number

San Francisco Bay Area

• Multiple Chips Timing Closure (SPARC Processor)- Experience on chip level timing closure methodology among power efficient and high performance chips. - Lead static timing analysis for ASIC, SOC, Scan/Sys/Tck domains..
• UPF Flow For Power Awareness in Primetime- Implement Synopsys golden UPF flow with simplified timing model generation and enable cross power domain timing analysis.- Provide optimized solution for categorizing cells in.
• Hierarchical ECO Flow For Control Block (DC/ICC)- Develop hierarchical ECO flow for physical ECO in late design stage. - Provide solutions for implementing ECO in desired control block inside hierarchical blocks, while.
• Software in Silicon - LLVM/Clang Compiler Bring Up- Configure and build LLVM/Clang compiler on version 3.8.1 & 3.9.1 in Linux from source.- Benchmark with turned flags for Spec CPU2006 across various Linux on SPARC.
• Develop recipe of fix_eco_timing from Synopsys with optimized fixing rate and lower eco cell count. Deliver test case for PrimeTime tool improvement on fixing rate among low slack paths.
• Deliver recipe for DMSA(Distributed Multi-Scenario Analysis) with proper fixing sequence of methods, among various hierarchical designs. Evaluate results between DMSA and in-house hold fixing tool.

San Francisco Bay Area

• Chip Bus Planning & Customized Routing- Plan and optimize Serdes buses with consideration of shielding and limited channel width. - Customize bus routing with Cadence CCT for over 6000+ nets. - Achieve balanced signal.
• Library Characterization & Flow Development- Develop and enhance library characterization flow for execution in batch mode. - Improve productivity and reduce duty cycle by parallel execution instead of serial mode..

Greater Los Angeles Area

Worked as a graduate assistant to grade course that involved integrated-circuit technologies for mixed-signal communication and data systems, constituent device models and their limitations, and contemporary research topics.

Master Of Science (Ms), Electrical Engineering - Vlsi, 3.96/4.0

Bachelor Of Engineering - Be, Electrical And Electronics Engineering, 3.7/4.0

Ranking: 1/127

Exchange Student, Electrical And Electronics Engineering

Selected among top 4% of students for one semester of knowledge share and learning.