Sergio V.
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Sergio V. Email & Phone Number

Computer Engineer | FPGA, ASIC design, test environments at Cadence Design Systems
Location: São Paulo, São Paulo, Brazil 6 work roles 2 schools
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✓ Verified May 2026 3 data sources Profile completeness 86%

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Current company
Cadence Design Systems
Role
Computer Engineer | FPGA, ASIC design, test environments
Location
São Paulo, São Paulo, Brazil
Company size
10 employees

Who is Sergio V.? Overview

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Quick answer

Sergio V. is listed as Computer Engineer | FPGA, ASIC design, test environments at Cadence Design Systems, a company with 10 employees, based in São Paulo, São Paulo, Brazil. AeroLeads shows a matched LinkedIn profile for Sergio V..

Sergio V. previously worked as Sr. Solutions Engineer at Cadence Design Systems and Test Analyst at Lumentum. Sergio V. holds Ci Brasil Program, Digital Ic Design from Escola Politécnica Da Usp.

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Email format at Cadence Design Systems

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Cadence Design Systems

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About Sergio V.

I am a graduate in Computer Engineering with experience in hardware development. During my undergraduate years, I worked in research projects on the study and simulation of integratedsystems and Networks-on-Chip on FPGA, at the Laboratory of Embedded and DistributedSystems (LEDS).After graduating, I joined the CI Brasil program, where I learned how to perform every step of designing and verifying a digital integrated circuit. During this program, I also participated in the design of a Bluetooth LE 5.0 device, from the study of the specification to the physical synthesis.

Current workplace

Sergio V.'s current company

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Cadence Design Systems
Cadence Design Systems
Computer Engineer | FPGA, ASIC design, test environments
sweden
Website
cadence.se
Employees
10
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6 roles

Sergio V. work experience

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Test Analyst

Lumentum

Campinas, São Paulo, Brazil

May 2021 - Aug 2024

Digital Ic Design Trainee

Lsi-Usp

São Paulo Area, Brazil

I worked on the project for a Bluetooth LE 5.0 device, where I developed the data parsing and processing for the link layer, and its verification environment.I also got experience with the logic and physical synthesis tools from Cadence and Synopsys, and learned how to build a verification environment using UVM methodology.

Apr 2019 - Mar 2020

Undergraduate Researcher

Universidade Do Vale Do Itajaí

Laboratory Of Embedded And Distributed Systems | LEDS

Project: Internal Traffic Analysis in a Network-on-Chip through Simulation

Aug 2016 - Jul 2017

Undergraduate Researcher

Universidade Do Vale Do Itajaí

Laboratory Of Embedded And Distributed Systems | LEDS

Project: Production of Instructional Material for the RedScarf Framework

Aug 2015 - Jul 2016
Team & coworkers

Colleagues at Cadence Design Systems

Other employees you can reach at cadence.se. View company contacts for 10 employees →

RS Ranjith Sankaranarayanan Ranjith Sankaranarayanan Colleague at Cadence Design Systems Bengaluru, Karnataka, India, India View → PK Prashant Kaushik Prashant Kaushik Colleague at Cadence Design Systems Pune, Maharashtra, India, India View → SP Sridhar Pathi Sridhar Pathi Colleague at Cadence Design Systems United States, United States View → 刘 刘运花 刘运花 Colleague at Cadence Design Systems China, China View → MF Matthew Fan Matthew Fan Colleague at Cadence Design Systems San Jose, California, United States, United States View → KL Kyle Lake Kyle Lake Colleague at Cadence Design Systems Portland, Oregon, United States, United States View → KT Kwang Tatt Loo Kwang Tatt Loo Colleague at Cadence Design Systems Singapore, Singapore View → SH Shannon Hash Shannon Hash Colleague at Cadence Design Systems Oklahoma City, Oklahoma, United States, United States View → FG Flowers Gus Flowers Gus Colleague at Cadence Design Systems Hanoi, Hanoi, Vietnam, Viet Nam View → VS Vinaya Singh Vinaya Singh Colleague at Cadence Design Systems Noida, Uttar Pradesh, India, India View →
2 education records

Sergio V. education

Ci Brasil Program, Digital Ic Design

Escola Politécnica Da Usp

A government program for training hardware designers through every step of a project, from a high level specification to the physical.

FAQ

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What company does Sergio V. work for?

Sergio V. works for Cadence Design Systems.

What is Sergio V.'s role at Cadence Design Systems?

Sergio V. is listed as Computer Engineer | FPGA, ASIC design, test environments at Cadence Design Systems.

Where is Sergio V. based?

Sergio V. is based in São Paulo, São Paulo, Brazil while working with Cadence Design Systems.

What companies has Sergio V. worked for?

Sergio V. has worked for Cadence Design Systems, Lumentum, Digesto Pesquisa E Banco De Dados, Lsi-Usp, and Universidade Do Vale Do Itajaí.

Who are Sergio V.'s colleagues at Cadence Design Systems?

Sergio V.'s colleagues at Cadence Design Systems include Ranjith Sankaranarayanan, Prashant Kaushik, Sridhar Pathi, 刘运花, and Matthew Fan.

How can I contact Sergio V.?

You can use AeroLeads to view verified contact signals for Sergio V. at Cadence Design Systems, including work email, phone, and LinkedIn data when available.

What schools did Sergio V. attend?

Sergio V. holds Ci Brasil Program, Digital Ic Design from Escola Politécnica Da Usp.

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