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@nvidia.com
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1 phone found area 612
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Setu Gupta is listed as Senior ASIC Design Engineer at NVIDIA at NVIDIA, based in Santa Clara, California, United States. AeroLeads shows a work email signal at nvidia.com, phone signal with area code 612, and a matched LinkedIn profile for Setu Gupta.
Setu Gupta previously worked as Senior ASIC Design Engineer at Nvidia and ASIC Design Engineer at Nvidia. Setu Gupta holds Certificate Of Specialization In Leadership & Management, Organizational Leadership from Harvard Business School Online.
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AeroLeads found 2 current-domain work email signals for Setu Gupta. Compare company email patterns before reaching out.
* Over 10 years of work-experience in SOC Design on 28/16/10/7 nanometer technologies at NVIDIA* Extensive graduate coursework in VLSI Design, CAD and front end at UMN.* Over 2 years of work-experience in production chips on 28nm SoCs at Qualcomm.* Strong academic background with research aptitude.* Flair for techno-entrepreneurship and corporate business innovation.Aim:- To build up a strong base to lead execution and delivery of quality silicon products and add value for the organization.- To be novel and innovative at work and strive to find new opportunities for improvement and growth.- To excel and adapt with changing VLSI paradigm, process technology and new market needs.Specialties: Recent Industry experience in:* Padring and IO-DFT logic* Spyglass Lint flow* Library verilog model & release management* Scripting & Design AutomationAcademic Experience in:* Custom Circuit Design* Architecture* CADBlock & Top Level Industry Experience in :* Static Timing Analysis and Timing Closure* Timing Constraints & Constraints Management* Automation in TCL & Perl* ECO Implementation* Formal Verification* Exposure to Embedded Software & Hardware Software Interfacing.
Listed skills include Tcl, Perl, Verilog, Embedded Systems, and 28 others.
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A career timeline built from the work history available for this profile.
Santa Clara, CA, US
GPU SOC Design *Padring for interfaces such as DDR, PCIE, NVMe, GPIOs *Verilog Library, Technology Library Model Integration *Farm Infrastructure & Build Automation *Spyglass LINT *RTL Integration
Minneapolis And St. Paul, Minnesota, US
In my graduate studies at University of Minnesota, I worked on following projects with a broad focus on concepts in Custom ASIC Macro Design, Synthesis & Technology Mapping (CAD view), ARM AMBA AHB System and Variation Tolerant Near Threshold Computing. 1 6T SRAM MACRO Design2 TMSuper, A novel technology mapper3 AMBA AHB System Design & Implementation4.
Santa Clara, CA, US
The internship assignment focuses on development and automation of power flow in existing clock flow at RTL stage and verifying and correlating the pre-layout and post-layout power estimates, including spice characterization of clock macros. This allows a good power estimation in the early phases of clock RTL generation.
San Diego, CA, US
*Design Synthesis*Timing Constraints & Constraints Management*Static Timing Analysis and Closure Support*Formal Verification (Constraints & Debug)*ECO Implementation*TCL/PERL Scripting & Automations *RTL Design
San Diego, CA, US
*Design Synthesis*Timing Constraints & Constraints Management*Static Timing Analysis and Closure Support*Formal Verification (Constraints & Debug)*ECO Implementation*TCL/PERL Scripting & Automations
San Diego, CA, US
*Path MTU Discovery and Protocol Stack Development for ARM based Mobile Chipsets.*Implementation of RFC 1981 in TCP/IP Stack of mobile software.*A software state machine, programmed in C.
*WSN Application for Planetary Explorations*First experimental prototype involving accelerometer, temperature and light sensor interfaced to AVR microcontroller.*Multihop sensor networking and Custom PCB designs for future work.*http://www.youtube.com/watch?v=cuAKuOCjaA0
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Vukasin Milovanovic
Colleague at Nvidia
Santa Clara, California, United States, United States
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Ginat Weisberg
Colleague at Nvidia
West Jerusalem, Jerusalem District, Israel, Israel
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Vaishnavi Bhore
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Pune, Maharashtra, India, India
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Eric Wilson
Colleague at Nvidia
United States, United States
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Onkar K.
Colleague at Nvidia
San Francisco Bay Area, United States
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Guangying Jiang
Colleague at Nvidia
San Jose, California, United States, United States
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Tirth Pandya
Colleague at Nvidia
San Jose, California, United States, United States
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Michal Pereg
Colleague at Nvidia
Israel, Israel
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Guilin Zhu
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Wan Chai, Hong Kong SAR, Hong Kong
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Eric Wu
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Taiwan, Taiwan, Province Of China
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Quick answers generated from the profile data available on this page.
Setu Gupta works for NVIDIA.
Setu Gupta is listed as Senior ASIC Design Engineer at NVIDIA at NVIDIA.
AeroLeads has found 2 work email signals at @nvidia.com for Setu Gupta at NVIDIA.
AeroLeads has found 1 phone signal(s) with area code 612 for Setu Gupta at NVIDIA.
Setu Gupta is based in Santa Clara, California, United States while working with NVIDIA.
Setu Gupta has worked for Nvidia, University Of Minnesota, Qualcomm, and Embedded Systems And Sensor Networks Research Group, Da-Iict.
Setu Gupta's colleagues at NVIDIA include Vukasin Milovanovic, Ginat Weisberg, Vaishnavi Bhore, Eric Wilson, and Onkar K..
You can use AeroLeads to view verified contact signals for Setu Gupta at NVIDIA, including work email, phone, and LinkedIn data when available.
Setu Gupta holds Certificate Of Specialization In Leadership & Management, Organizational Leadership from Harvard Business School Online.
Setu Gupta is listed with skills including Tcl, Perl, Verilog, Embedded Systems, Spice, Vhdl, Soc, and Cadence Virtuoso.
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