Stephen Fischer Email & Phone Number

Milpitas, CA, US

Leading cPacket's FPGA team developing 100Gbps line rate packet brokering and network analytics solutions, enabling our customers to perform high-fidelity packet observation, advanced processing, and intelligent delivery to dashboards, security tools, and performance management tools.We are hiring!

Systems engineering and FPGA consultant at an early-stage stealth-mode startup, working on a CXL device to enable composable architectures.

• Joined Memory Solutions Lab, an advanced R&D organization for memory and data center technologies, to work on architectures and innovations for flash storage, and ultimately led a team to develop the SmartSSD.
• Managed team of 30+ engineers working on research and prototyping of innovative storage solutions, and productization of SmartSSD, a trailblazing computational storage device.
• Led architecture, FPGA/software/firmware development and system integration/test for SmartSSD, enabling industry ramp of new intelligent storage solutions for near-data processing at data center scale.
• Developed use cases and identified and built relationships with solution partners to create market opportunities, show performance benefits and demonstrate customer value for a new product class.
• Established partnership with Xilinx, leading to business agreement, and coordinated 4-way collaboration between Samsung US/Korea and Xilinx US/India on co-development, test and debug of SmartSSD.
• Built and managed relationships with leaders/teams in Korea, IP/university partners & lead customers.

• Led team of 10+ FPGA and embedded software engineers working on SmartSSD proof-of-concept development and lab testing.

• Led technical effort to debug and stabilize FPGA data path on Ethernet SSD project resulting in successful demonstration of NVMe over fabric (NVMeoF).
• Led architecture, feasibility study, performance characterization and vendor collaboration for AMD EPYC CPU based high-performance 1U storage server, to achieve industry-leading storage/network density.
• Developed architecture and lab prototype of a 4-node high-availability storage platform with 24 dual-port NVMe SSDs and an adaptive PCIe switch fabric, demonstrating 100% performance after failover.

• Joined start-up after ~2.5 years of operations, to lead systems and hardware organization to harden the company’s first generation peta-scale blade-based flash storage array for initial customer deployments and to help.
• Led organization of HW and SW driver/diagnostics engineers developing a multi-petabyte flash array incorporating custom Intel motherboards and off-the-shelf flash modules running custom firmware.
• Managed relationship with partner company in Taiwan to co-develop a custom Intel Haswell CPU based motherboard supporting PCIe hot-pluggable cartridges each containing multiple m.2 flash modules.
• Led team to root cause hardware failures in the field and document failure analyses.
• Led team to develop and implement tests for stressing the array’s hardware modules, in particular the power hold unit which incorporated 200+ supercapacitors.
• Led hardware development project for second generation array, driving for improvement of architecture, design, cost, reliability and manufacturability over the first generation array.

Colorado Springs, Colorado, US

Joined on first day of funded operations to lead architecture and hardware/firmware development of a scalable memory technology, from concept to technology demo to DRAM array to four generations of flash array. Held various leadership roles as company grew to 400+ employees and $100M/year revenue.* Led organization of 40+ hardware engineers, FPGA.

Colorado Springs, Colorado, US

• Led team of 10+ hardware and FPGA engineers to productize a 19nm flash memory module, resulting in a substantial increase in product profit margins.
• Led FPGA architecture, development and test of the non-disruptive array upgrade feature.
• Invented, architected and led development of a custom data redundancy/reliability feature resulting in a reduction in data path related customer escalations.
• Trained sustaining engineers to take over customer escalations related to FPGA data path.
• Hands-on experience with test and characterization of multiple generations of flash from multi vendors.

Colorado Springs, Colorado, US

• Built and led a high caliber HW/FPGA team to architect and design Violin’s DRAM array, first and second generation flash arrays, and flash/RAID modules for third-gen flash array.
• Managed SW, QA, release-eng and manufacturing during periods of leadership transition.
• Prioritized tasks to deliver high quality products/releases on tight schedules with limited resources.
• Hands-on debug of complex QA issues, and resolution of customer data path escalations.
• Negotiated with vendors for contracts/pricing on hardware components and tools.

San Jose, California, US

• Led the hardware/FPGA team to architect and develop a 400 Gbps multi-protocol packet switch.
• Architecture for FPGA based packet processing engines supporting MPLS, IPv4/IPv6 and Ethernet with advanced filtering, policing, shaping and queueing features for QoS.
• Verification of inter-connected FPGAs and ASICs using VHDL testbench and python scripts.
• Developed methodology and scripts for automation of FPGA build/simulation, FPGA pin assignments, code generation for packet/memory structures and PCB netlist verification.

San Jose, California, US

Joined early stage startup as first non-founder HW engineer, to work on FPGA architecture/design for high speed packet processing. Received multiple promotions with expanded leadership responsibilities.Xebeo Communications was acquired by UTStarcom.

• Joined early stage startup as one of first four non-founding engineers to help architect content distribution and switching infrastructure for video-on-demand services.
• Hardware architecture for next generation multi-service, broadband access equipment.

Espoo, Southern Finland, FI

• Joined a startup-like project to work on architecture/design for an IP router with advanced QoS features.
• Architecture for next generation OC192 SONET/IP/MPLS multi-service switching product.
• FPGA design, verification and lab debug for scheduler FPGA and switch fabric interface FPGAs.

Research on multiple access control protocols for indoor wireless ATM LANs.

Ph.D., Electrical Engineering

Be, Electrical And Electronics Engineering