Shaiful Alam Email & Phone Number

Austin, Tx, Us

Austin, Tx, Us

Santa Clara, California, Us

Currently serving as the SOC full chip timing lead for Intel's 5G network infrastructure product portfolio chips.Successfully managed the tape-out process for five large SOC designs (> 200 million) on cutting-edge technology nodes.Key Responsibilities:* Developed and optimized flow, methodology, and timing closure planning, while constructing and refining timing models to achieve final signoff.* Collaborated closely with cross-functional teams including physical designers, clock, RTL, DFT, and IP teams to troubleshoot clocking, constraints, UPF, and collateral issues crucial for timing closure.* Worked in tandem with full chip and partition physical designers to address timing quality of results (QOR), unclocked sequential, DRC, crosstalk, parasitic annotation, UPF, constraint issues, and IO budgeting for design convergence.• Developed and implemented numerous timing/power ECOs to achieve design convergence throughout project execution.These experiences have sharpened my skill in navigating the intricate challenges inherent in full chip timing closure, leading to optimal outcomes in high-stakes SOC projects.

Santa Clara, Ca, Us

Physical Design Manager and project lead for multiple cellular and application processor chips (ARM based dual, tri, quad and octa core SOCs) from different technology nodes.Sr. Staff physical design engineer lead performed full chip SOC backend design activities for cellular and application processor chips from different technology nodes. Responsibilities include top level UPF flow development, placement and timing optimization, clock tree synthesis, multi-VDD routing, ECO and timing closure.

Santa Clara, California, Us

• Performed synthesis in DC/Blast, multi-VDD placement, CTS, routing, STA, scan insertion on multi-million gates design.• Developed a complete SOC implementation flow from RTL/Gate to GDSII using Magma tools Blast in the area of synthesis, placement, scan reordering, clock tree synthesis, multi-corner hold, xtalk delay and noise aware routing, bonus cell placement, multi-VDD routing flow for physical design team.

• As an in-house expert for FPGA design tools (synthesis and place and route), performed beta testing and provided guidelines to EDA vendors to improve QOR.• Performed competitive analysis with a list of design by running synthesis, place & route in the FPGA marketplace.• Provided pre and post-sales support to the customers designing FPGA (related to synthesis, place-and-route, timing closure, device failure etc).

Msee, Advanced Computer Archicture And Electronics

Bsee, Electrical And Electronics