AeroLeads people directory · profile

Shaiful Alam Email & Phone Number

SOC Timing Lead driving STA flow and methodology, timing closure for advanced technology nodes. at Intel Corporation
Location: Austin, Texas, United States 5 work roles 2 schools
1 work email found @intel.com LinkedIn matched
✓ Verified May 2026 4 data sources Profile completeness 86%

Contact Signals · 1 work email

Work email s****@intel.com
LinkedIn Profile matched
3 free lookups remaining · No credit card
Current company
Intel Corporation
Role
SOC Timing Lead driving STA flow and methodology, timing closure for advanced technology nodes.
Location
Austin, Texas, United States
Company size
114813 employees

Who is Shaiful Alam? Overview

A concise factual answer block for searchers comparing this professional profile.

Quick answer

Shaiful Alam is listed as SOC Timing Lead driving STA flow and methodology, timing closure for advanced technology nodes. at Intel Corporation, a company with 114813 employees, based in Austin, Texas, United States. AeroLeads shows a work email signal at intel.com and a matched LinkedIn profile for Shaiful Alam.

Shaiful Alam previously worked as Full chip Timing Lead at Intel Corporation and Physical Design Manager/Sr. Staff Physical Design Engineer at Marvell Semiconductor, Inc. Shaiful Alam holds Msee, Advanced Computer Archicture And Electronics from Wichita State University.

Company email context

Email format at Intel Corporation

This section adds company-level context without repeating Shaiful Alam's masked contact details.

{first}.{last}@intel.com
89% confidence

AeroLeads found 1 current-domain work email signal for Shaiful Alam. Compare company email patterns before reaching out.

View email format View company profile Management contacts
Profile bio

About Shaiful Alam

As the Full Chip Timing Lead at Intel Corporation, I leverage over 20 years of expertise in physical design, synthesis, and static timing to deliver cutting-edge SOCs for advanced technology nodes and flagship products. My specialties include block and full chip STA flow, timing closure, power optimization, and ECO.In my current role, I lead the full chip timing team, overseeing the STA flow and methodology for various Intel SOCs, including the pivotal 5G network infrastructure SOC. I'm accountable for timing closure, signoff, ECO, and methodology enhancement. Collaborating with cross-functional teams, I ensure SOC quality and reliability, tackling complex timing challenges. I've successfully delivered flagship products like cellular and application processor chips, and server CPU SOCs. My goal is to exceed customer expectations, elevate industry standards, and contribute to Intel's leadership in the semiconductor realm.Specialties: * Proficient in full chip Static Timing Analysis (STA) and design closure for multi-million gates. * Expertise in Logical & Physical Synthesis, Place & Route (APR), CTS, parasitic extraction, and ECO flow. * Skilled in SOC flow development from RTL to GDS.

Current workplace

Shaiful Alam's current company

Company context helps verify the profile and gives searchers a useful next step.

Intel Corporation
Intel Corporation
SOC Timing Lead driving STA flow and methodology, timing closure for advanced technology nodes.
Austin, TX, US
Website
intel.com
Employees
114813
AeroLeads page
Company profile
View company profile Email format
5 roles · 29 years

Shaiful Alam work experience

A career timeline built from the work history available for this profile.

Full Chip Timing Lead

Current
Intel Corporation

Santa Clara, California, US

  • Currently serving as the SOC full chip timing lead for Intel's 5G network infrastructure product portfolio chips.Successfully managed the tape-out process for five large SOC designs (> 200 million) on cutting-edge.
  • Developed and implemented numerous timing/power ECOs to achieve design convergence throughout project execution.These experiences have sharpened my skill in navigating the intricate challenges inherent in full chip.
2015 - Present ~11 yrs 4 mos

Physical Design Manager/Sr. Staff Physical Design Engineer

Marvell Semiconductor, Inc

Santa Clara, CA, US

Physical Design Manager and project lead for multiple cellular and application processor chips (ARM based dual, tri, quad and octa core SOCs) from different technology nodes.Sr. Staff physical design engineer lead performed full chip SOC backend design activities for cellular and application processor chips from different technology nodes. Responsibilities.

2006 - 2015 ~9 yrs

Staff Physical Design/Cad Engineer

Intel Corporation

Santa Clara, California, US

  • Performed synthesis in DC/Blast, multi-VDD placement, CTS, routing, STA, scan insertion on multi-million gates design.
  • Developed a complete SOC implementation flow from RTL/Gate to GDSII using Magma tools Blast in the area of synthesis, placement, scan reordering, clock tree synthesis, multi-corner hold, xtalk delay and noise aware.
2002 - 2006 ~4 yrs

Sr. Technical Marketing/Applications Engineer

Actel Semiconductor
  • As an in-house expert for FPGA design tools (synthesis and place and route), performed beta testing and provided guidelines to EDA vendors to improve QOR.
  • Performed competitive analysis with a list of design by running synthesis, place & route in the FPGA marketplace.
  • Provided pre and post-sales support to the customers designing FPGA (related to synthesis, place-and-route, timing closure, device failure etc).
1997 - 2001 ~4 yrs
Team & coworkers

Colleagues at Intel Corporation

Other employees you can reach at intel.com. View company contacts for 114813 employees →

NP Nadeen Paradis Nadeen Paradis Colleague at Intel Corporation Scottsdale, Arizona, United States, United States View → WW William Wang William Wang Colleague at Intel Corporation San Jose, California, United States, United States View → AA André Arias Ovares André Arias Ovares Colleague at Intel Corporation Cartago, Costa Rica, Costa Rica View → EB Eric Bustillo Eric Bustillo Colleague at Intel Corporation Hillsboro, Oregon, United States, United States View → DA Dr. Abdallah Bacha Dr. Abdallah Bacha Colleague at Intel Corporation Germany, Germany View → NN Nevine Nassif Nevine Nassif Colleague at Intel Corporation Arlington, Massachusetts, United States, United States View → AS Ahmad Sufian Ahmad Sufian Colleague at Intel Corporation Kulim District, Kedah, Malaysia, Malaysia View → TS Trisha Sparacino Trisha Sparacino Colleague at Intel Corporation San Jose, California, United States, United States View → KS Kalan Schwarting Kalan Schwarting Colleague at Intel Corporation Greater Phoenix Area, United States View → VD Vinod Durga Vinod Durga Colleague at Intel Corporation Bengaluru, Karnataka, India, India View →
2 education records

Shaiful Alam education

Msee, Advanced Computer Archicture And Electronics

Wichita State University

Bsee, Electrical And Electronics

Bangladesh University Of Engineering And Technology
FAQ

Frequently asked questions about Shaiful Alam

Quick answers generated from the profile data available on this page.

What company does Shaiful Alam work for?

Shaiful Alam works for Intel Corporation.

What is Shaiful Alam's role at Intel Corporation?

Shaiful Alam is listed as SOC Timing Lead driving STA flow and methodology, timing closure for advanced technology nodes. at Intel Corporation.

What is Shaiful Alam's email address?

AeroLeads has found 1 work email signal at @intel.com for Shaiful Alam at Intel Corporation.

Where is Shaiful Alam based?

Shaiful Alam is based in Austin, Texas, United States while working with Intel Corporation.

What companies has Shaiful Alam worked for?

Shaiful Alam has worked for Intel Corporation, Marvell Semiconductor, Inc, and Actel Semiconductor.

Who are Shaiful Alam's colleagues at Intel Corporation?

Shaiful Alam's colleagues at Intel Corporation include Nadeen Paradis, William Wang, André Arias Ovares, Eric Bustillo, and Dr. Abdallah Bacha.

How can I contact Shaiful Alam?

You can use AeroLeads to view verified contact signals for Shaiful Alam at Intel Corporation, including work email, phone, and LinkedIn data when available.

What schools did Shaiful Alam attend?

Shaiful Alam holds Msee, Advanced Computer Archicture And Electronics from Wichita State University.

Find 750M verified contacts

Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.