Shaikh Arif Shams, Ms Email & Phone Number

Santa Clara, Ca, Us

Architect and Design IPs - LVDS, SSTL, GPIO, PCI66, LDO etc.

Reading, England, Gb

Develop AMS verification testbenches for chargers used inside smartphones.

San Diego, Ca, Us

• Designed voltage regulator in 7nm 116GB/s PAM4 High Speed Serial Link for transmitter and receiver clocks. o Designed on both GF process and TSMC process. o Compared different topologies and chose the best one for the purpose at hand with the constraints faced. It required analysis using small signal models of the devices relating to design specification.o Characterized all the available device types to choose the most optimum device type to use in the design o Design work included Spice/Spectre/APS simulations using Cadence ADEXL/ADE, floor planning, layout supervision, post-layout extraction, reliability (Electromigration, Self-Heat, IR drop) simulation activities.• Designed clock driver in 14nm 56GB/s PAM4 High Speed Serial Link for receiver.o Design work included Spice/Spectre/APS simulations using Cadence ADE, MDL, floor planning, layout supervision, post-layout extraction, reliability (EM, SH, IR drop) simulation activities.o Planned wide varieties of simulations including Jitter, Duty Cycle Distortion measurements with power supply noise and executed on the plan.Key Achievements• Highly efficient and stable regulator design achieving high PSRR and occupying small area attracted several other teams. Helped them adopt this architecture and design.• Developed the package requirements document used by customers to design their package and meet the challenging demand of high speed interfaces.

Santa Clara, California, Us

High-Speed Serial IO Receiver Design• Designed activity detector/wake-up circuits (squelch in PCIE and SATA; LFPS in USB3.x) and DFx (Design for Test/Manufacturing/Debug) circuitry on 32nm, 14nm and 10nm CMOS processes. o Design work included behavioral modeling, Spice/Mixed-signal simulations using Cadence ADEXL/ADE, floor planning, layout supervision and post-layout extraction activities. o Worked on Post Silicon Electrical Validation of the same.• Led the Pre-Si Validation of the High-speed Serial IO receiver covering functional verification using XA/Ultrasim, AMS, Formal Verification, reliability verification (Electromigration, Self-heat), Electrical Over Stress (EOS), Aging and Burn-in simulations, ERC (Electrical Rule Checker), SRC (Schematic Rule Checker), QA. Conducted statistical analysis with the variations in gate length and thresholds on circuit performance and validating schematics with their behavioral models. • Developed behavioral model of the entire receiver in the 10nm project. • Worked on the power supply current profile (Icc(t)) of the chip for its power delivery. • Used Agile project management, Scrum in the projects.Key Achievements• Tackled the challenge of meeting overlapping specs of low-frequency detection and high-frequency rejection in LFPS by utilizing circuit techniques on analog front and incorporating controls on digital front.• Devised design approach to ensure device junction voltages do not exceed allowed voltage limits in a high power supply.• Validation Lead -- Collaborated with the tools and methodologies team as a subject matter expert and assisted the team in the enhancement of innovative 32nm and 14nm project tools and methodologies adopted by all future projects.

Santa Clara, California, Us

Chipset Design on 45nm Process• Designed Current Mode Logic (CML) level clock distribution network, PLLEBB and Compensation block (ICOMP and RCOMP) for QuickPath Interconnect QPI (3.2GHz Clk speed). The design included differential amplifier buffers, analog multiplexers, and high-speed dividers. Conducted validation using Tango, Ultrasim, ERC of PLLEBB and Compensation block (ICOMP and RCOMP) in QPI (QuickPath Interconnect). • Led Pre-Si Validation of QPI Transmitter (TX), PLLEBB and compensation block and the Reliability Verification of the entire QPI. • Worked on Post-Si Electrical Validation of QPI Transmitter (TX), PLLEBB and compensation block involving FIBing and pico-probing. Analog Engineer -- Chipset Design on 45nm Process (continued)Key Achievements• During validation of an external Intel chipset project, Identified and determined the root cause of numerous bugs in the chip, which included op-amp stability, DCC stability, narrow hold margins, narrow clock routing, and insufficient vias, documented and submitted bugs to the design team for resolution.

Santa Clara, California, Us

Chipset Design on 65nm Process (08/2005 to 01/2007)• Designed PCI, GPIO, APSM, Fuse EBB and HVSYNC, wrote CAS and delivered lib files. • Designed the fuse read logic to meet the timing spec. o Worked on fuse placement inside core targeted to die size reduction. • Worked on LVS QA of special devices (GBNWELL, VDNMOS etc.) tolerant to high voltages.

Santa Clara, California, Us

Standard Cell Library and ROM Compiler Development• Developed standard cell libraries (1000+ standard cells) for the 65nm and 90nm processes. • Conducted Spice simulation and Optim2 to size devices in the standard cells. • Characterized standard cells using IDEAL II and released Verilog and Synopsys libraries along with other views/models used by the customers.Key Achievements• Earned the Divisional Recognition Award for delivering multiple high-quality Standard Cell Libraries. • Converted the ROM characterization flow from Ocean to Perl that reduced the characterization time by more than 50X

Santa Clara, California, Us

• Logic Verification (LVR) of Madison, 64-bit microprocessor of Itanium family. o Conducted simulations on the circuit model built using “Shark” tool. o Ran LVR on Data Control Cluster and full-chip. o Developed the behavioral model of Level 1 Data Cache that reduced the simulation run time and the initialization sequence cycle count significantly. • Wrote RTL of Madison clock unit ( a complex mixture of analog/digital circuitry).

Master Of Science (Ms), Electrical And Computer Engineering

Bachelor Of Science, Electrical And Electronic Engineering