Shalini Suresh Email & Phone Number

San Jose, CA, US

Working with the system level verification team supporting pre-silicon testing of Ethernet packet processor and switching ASICs.

- Currently working on verifying DMA blocks which transfer data between host or on-chip memory and DDR. - Worked on block level verification for Converged network adaptor. Verification process includes development of constrained random environment in System Verilog based on VMM, identifying and tracking bugs and identifying completion based on functional.

Ahmedabad, Gujarat, IN

Role involved supporting hardware design and verification clients in the Bay Area.

San Jose, CA, US

Role involved developing module level design verification environment in System Verilog using VMM concepts. The environment classes extend Cisco’s library of classes extended from VMM base classes. This involves creating a self-checking constrained random test bench, helping in test plan development, working with designer in resolving bugs and.

Wilmington, DE, US

Verification lead for multiple RTL blocks in a WCDMA Release 6 modem.Blocks tested include:Timing Manager, SMA Controller, and Rx Chip. Each of the blocks had its own testing methodology like randomized testing using AVM with System Verilog for SMA; VHDL timing based testing for timing manager and Bit Accurate Verification (BAV) for Rx chip.Role involved.

Wilmington, DE, US

Role was to develop RTL blocks using VHDL. The key block worked on was a Memory System Controller (MSC). The MSC is a command sequencer and arbiter for a set of components to access the memory in a 3G UMTS modem. The subtasks included design, development, and verification of the MSC. Another key responsibility was working with architecture and design teams.

Wilmington, DE, US

Role consisted of developing VHDL test benches for RTL component blocks, executing the tests and supporting issues identification, debug and resolution efforts.

Wilmington, MA, US

Role consisted of developing behavioral Verilog and timing models for a timing vernier test chip in Primetime. The timing vernier was designed to generate signals whose timing is set by the user and also can be calibrated by the user and used mainly for ATE. The stamp modeling technique in Primetime was used to develop the timing models. Responsibilities.

M.S, Computer Engineering

B.E, Electronics And Communication Engineering

High School