> Front end Implementation engineer responsible for the synthesis of WiFi Access point chips. > Actively involved in PPA optimization, STA, formal verification, low power checks, power estimation at RTL, synthesis and Post PnR stages. > Expertise in timing closure, synthesis debugs and power and area optimization.> Proficiency in python and TCL scripting.

> Expertise on synthesis of High-speed and Low-power datapath wireless modem chip designs.> Proficiency in PPA analysis and optimization.> Strong command on netlists and UPF.

> Learning on UVM testbench design with APB interface using System Verilog and verification of the same by assertion methodology> Expertise on creating advanced HTML dashboard using Python, CSS, and JavaScript to display verification data