Yossi Shanava Email and Phone Number
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Season ASIC/FPGA design professional with proven extensive experience in the entire aspects of ASIC design process, from micro-architecture definition, RTL coding, verification, implementation to tape out and validation. Successfully led and designed a large number of SoC for AI self driving cars, Data servers, base stations, security network processors and high power mix signal chips for PoE.Specialties: Data Cache Design, scatter/gatter accelerators, 3G/4G/5G Mobile Broadband Protocols, HFA Hyper Finite Automata, HNA/NFA - Hyper Non Deterministic Automata, Mix Signal Design, Traffic Manager, Networking and PoE (Power over Ethernet)
Deeproute.Ai
View- Website:
- deeproute.ai
- Employees:
- 94
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Deeproute.AiSanta Clara, Ca, Us
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Principal Design EngineerDeeproute.Ai Nov 2022 - PresentFremont, California, UsInvented fast sorting free, scatter op accelerator.Defined high speed, L zero that is optimized for gathering up to 64 addresses.Defined multi port, multi banks 32MB L2 Data cache.
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Sr. Principal EngineerPalo Alto Networks May 2021 - Oct 2022Santa Clara, California, UsHost interface, PCIE, chip level power on reset -
Senior Staff EngineerMarvell Semiconductor Feb 2010 - May 2021Santa Clara, Ca, Us-- Baseband phy 5G eCPRI compression decompression-- Multi ports, multi banks Data caching.-- Responsible for multi 3G blocks for base station chip.-- HNA - Hyper Non-deterministic Automata. Used for deep packet inspection (DPI) applications.-- HFA - Hyper Finite Automata. -
Staff Design EngineerAmcc Sep 2006 - Feb 2009Santa Clara, Ca, UsResponsible for Traffic Manager subsystem design and implementation in a highly integrated Soc. -
Senior Staff Design EngineerBroadcom Jan 2006 - Sep 2006Palo Alto, California, UsSupervised the digital development of SoC mix signal chip for PoE application. -
Asic Design EngineerPowerdsine Dec 2003 - Jan 2006Aliso Viejo, Ca, UsPrimarily responsible for designing the digital section of a mix signal chip, for a PD (Powered Device) application, from concept to silicon. -
Asic Design EngineerAmcc May 2000 - May 2003Santa Clara, Ca, UsParticipated in the development of four network processors for ATM and Ethernet up to 10Gb.Designed a wide variety of blocks through the stages: specification definition, RTL coding, verification, synthesis and static time analysis.
Yossi Shanava Skills
Yossi Shanava Education Details
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Technion - Israel Institute Of TechnologyElectrical Engineering
Frequently Asked Questions about Yossi Shanava
What company does Yossi Shanava work for?
Yossi Shanava works for Deeproute.ai
What is Yossi Shanava's role at the current company?
Yossi Shanava's current role is Principal Engineer at Deeproute.ai.
What is Yossi Shanava's email address?
Yossi Shanava's email address is yo****@****ium.com
What is Yossi Shanava's direct phone number?
Yossi Shanava's direct phone number is +140894*****
What schools did Yossi Shanava attend?
Yossi Shanava attended Technion - Israel Institute Of Technology.
What skills is Yossi Shanava known for?
Yossi Shanava has skills like Verilog, Asic, Soc, Rtl Design, Ic, Static Timing Analysis, Embedded Systems, Computer Architecture, Semiconductors, Networking, Ethernet, Perl.
Who are Yossi Shanava's colleagues?
Yossi Shanava's colleagues are Peishuo Wang, Can Zhu, 栗嘉琪, Tian W., Yi Li, Libing Zhang, Xiaowei Sheng.
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