SoC-level and block-level verification on multiple WD enterprise NAND-flash SSD Controllers.Led cross-site, cross-organizational team to integrate new encryption block into SoC. Scoped verification effort of several blocks from specs and interaction with RTL designers and architects, wrote and maintained verification specs and verification plans and was responsible for meeting schedules. Created, debugged & maintained clean-sheet and leveraged System Verilog UVM testbenches, wrote testcases and debugged regression failures, closed functional and code coverage. Verified integration of external company's IP into ASIC and worked with Taiwan- and India-based engineers, contractors and external vendors.Western Digital verification engineer embedded in HP-Enterprise's ASIC ReRAM Controller design team.Scoped tests of ReRAM-interfacing block, made schedule estimates, added environment features, wrote verification IP and sequences and debugged and fixed test failures. As point of contact for SanDisk BFM releases to customer, set up SFTP drop box and JIRA bug database, communicated customer feedback to resolve major release faults. Interviewed and on-boarded verification engineers.SoC-level and block-level verification on multiple WD enterprise NAND-flash SSD Controllers.Created, debugged & maintained clean-sheet and leveraged System Verilog UVM testbenches, wrote testcases and debugged regression failures, closed functional and code coverage. Verified integration of external company's IP into ASIC and worked with Taiwan- and India-based engineers, contractors and external vendors. Western Digital verification engineer embedded in HP-Enterprise's ASIC ReRAM Controller design team. Scoped tests of ReRAM-interfacing block, made schedule estimates, added environment features, wrote verification IP and sequences and debugged and fixed test failures. Skills: Verification Plan Creation · SoC Integration · Block IP Verification · SystemVerilog · UVM

Verified IP blocks for several Enterprise & Client SSD Controller ASIC designs, meeting or exceeding milestone requirements. Gathered requirements for, architected, implemented and debugged multiple verification environments and their components in UVM or VMM with System Verilog. Created and maintained verification plans, test plans and schedules. Interfaced with other groups delivering block IP and with system integration for methodology and delivery requirements. Wrote constrained random and directed test cases and analyzed and closed coverage.Selected accomplishments:• Led read datapath verification, delivering high quality RTL and verification IP (VIP) with system integration team integrated into chip-level environment.• Coordinated milestone releases to cross-site system integration team and periodically updated block IP environment with new vendor library cell releases, successfully releasing block IP to system integration at multiple milestones.• Wrote and maintained variety of UVM & VMM components, including constrained-random stimulus (sequences), scoreboards, data classes, transactors.

Improved the design flow for low power metering ASIC by converting hand instantiated logic into synthesizable Verilog and implementing a fully automated P&R flow. Introduced low power methodologies such as clock gating and scan across power/ clock domains. UPF flow from RTL to tapeout.

Various consulting jobs: Samsung Austin R&D Center• Intersil Corporation, Austin, TX• NXP Semiconductors, Tempe, AZ• FirstPass Engineering, Phoenix, AZ• ASIC North, Inc. Tempe, AZ• Microchip, Chandler, AZ• SEMTECH, Redondo Beach, CA• IBM, Burlington, VT• HemisphereGPS, Scottsdale AZ• Broadcom, Andover, MA• General Dynamics, Scottsdale, AZ