Shane Bentley Email & Phone Number

Melbourne, Australia

Melbourne, Australia

Melbourne, Australia

Carolton, Victoria, Australia

In January 2014 I joined Nitero as a Senior ASIC design and verification engineer. Nitero have implemented an 802.11ad MAC/Phy and RF compliant chip set. Our first 28nm silicon was functional and successful at Wi-Fi alliance interoperability testing. During my tenure at Nitero I have completed many tasks including: 1. Analysing and largely redesigning a WiGIG (802.11ad) LDPC decoder to be smaller in size and lower in power to meet target power budgets while maintaining the decoder's performance.2. I applied the above power analysis reduction process to many other modules in the 802.11ad baseband design including matching filters, a decision feedback equalizer, a soft-bit descrambler, and a sample rate converter. 3. I introduced 'Jenkins' Continuous Integration to manage all of our regression testing.4. I have implemented several support scripts to automate routine tasks such as FPGA synthesis, logging power analysis results an syncing backup data across sites.5. I have reviewed several of the engineering board designs to assist in locating errors before manufacture.6. I adopted the Systems Administration role and managed all of the digital team's servers and services.7. I have designed, modelled and implemented a video/image compression algorithm for fixed compression ratios with low latency for VR applications. The model was written in C/C++. The design was implemented in Verilog. The verification was implemented using PLI calls to the c-model to verify the Verilog implementation.8. The Compression algorithm was validated in an Ultra scale Xilinx FPGA development platform. I was responsible for implementing and automating the Synthesis flow with Vivado and controlling the release procedure of BIT files. This included tcl scripting for Vivado. The build flow was integrated into the Jenkins Continuous integration system to ensure that timing was always met and timing violations due to design changes were caught early.

Assignment 1ASIC Design and VerificationLocation: Lund, SwedenConsultant for Ericsson Mobile Platforms

At the beginning of February 2002 I began full time employment in CISRA’s Graduate program. In February 2003 I was promoted from an Associate ASIC design engineer to a Standard ASIC design engineer. I have worked in project teams of three to six people. I was involved in all aspects of the projects including Planning, Status reporting, Verification and project delivery.Projects: 1. Printer Engine controller, Half Toning and Pixel Delivery2. Hardware JPEG compressor/Printer controller3. 1394a Firewire4. USB Device Controller5. Page Analysis Algorithm