I work at the intersection of Semiconductor Product, Technology and Operations, creating innovative product solutions and building capabilities from the ground up that resolve complex challenges and grow business value. Leveraging an extensive leadership career in the semiconductor industry, I bring expertise in both execution-focused (volume manufacturing, NPI, quality) and exploration-focused teams (product definition, technology development, ecosystem enablement). Adept at cross-functional management and stakeholder alignment to drive product and business success.Noted for:ProductizationFounding member of Custom Silicon Operations team, recognized for engineering innovation and global leadership in launching four generations of networking ASICs in six years, supporting over ten different hardware product lines. Managed high volume scale (>$xB+ revenue), successfully navigating the semiconductor shortages by qualifying alternate sources, managing capacity planning and allocation, and optimizing manufacturing processes. AI and Robotics for OperationsPioneered the use of industry-first robots for high-volume ASIC testing, reducing test costs and increasing throughput by 10x. Developed a strategic plan for integrating AI and robotics into workforce strategy, pioneering use of cobots in lab environment for characterization, with projected ROI in double digits after first year. Created a comprehensive roadmap for Manufacturing Execution System (MES) and AI-based analytics to accelerate yield learning and incident response.Zero-to-One and ScaleLed teams through zero-to-one product launches and successfully managed ramp (four generations of ASICs, 40+ SKUs, 10+ hardware product lines). Built and scaled a multi-domain team for an acquisition that reshaped Cisco product strategy, growing from five to ~100 people globally. Technology Development and IncubationCo-developed materials, processes, and test infrastructure in partnership with supplier ecosystem as part of multi-year roadmap for sustained ASIC differentiation (electrical and thermo-mechanical) and operational metrics improvement (cycle time and yield).
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Product @ CspeedCspeed IncMountain View, Ca, Us -
Senior DirectorAstera Labs Dec 2024Santa Clara, California, United States -
Director, Silicon One ProductizationCisco 2018 - Dec 2024San Jose, California, United StatesDIRECTOR – SILICON ONE PRODUCTIZATION (2018 – Present)SENIOR MANAGER (2018 – 2021)Founding team member and intrapreneur tapped to lead ASICs from startup acquisition to production. Directly oversaw all technical operations activities post tape-out (test, product, assembly, foundry, reliability, sustain engineering) for four generations of ASICs scaling to >$xB+ in revenue. IMPACTInstrumental in setting up a foundational framework of milestones, processes, and metrics for New Product Introduction and end-to-end quality and engineering productivity management (supplier quality, manufacturing and test quality, customer quality) and capital and operational spend management ($xxxM). Managed high-volume scale through semiconductor shortages by qualifying alternate sources (~10+ routes per product), managing capacity planning and allocation, and optimizing manufacturing processes. Scaled a global, multidisciplinary team to ~100 members. Established site strategy and hired the first employees in four countries, building a cohesive team around these initial hires. -
Component And Product Engineering ManagerCisco 2015 - 2018San Jose, California, United StatesPromoted to manage merchant silicon quality during period of strong focus on off-the-shelf silicon. Developed and led team of eight engineers focused on component, supplier and product quality for ~$1.5B spend covering networking silicon, PHYs, FPGAs, and MCUs.IMPACTCustomized previous innovative methodologies (developed as Component Engineer) for time-to-quality volume and cost of quality management to scale across large and diverse supplier base. Created a robust supplier incubation framework for startups to scale successfully. Expanded scope to cover DSPs and drivers for optics, enabling merchant silicon startups with differentiated design to scale to volume meeting quality requirements. Resolved yield and quality bottlenecks to release three generations of products to production over a three-year period.
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Component EngineerCisco Systems 2012 - 2015San Francisco Bay AreaBrought in to drive new technologies and quality excellence to reduce cost of quality at the same time. Managed supplier quality, interacting with every major Semiconductor supplier worldwide, as well as setting up methodologies for fledging startups. Managed supplier quality for~$1B spend. IMPACTDrove supplier planning teams to align with Cisco NPI product ramp plans and resolved yield and burn-in bottlenecks to meet product timelines – meeting On-Time-Ship metric and Time-To-Market. Awarded Cisco’s Quality Innovation award (2014) for pioneering new methodology that demonstrated TTQ and TTM improvements of up to 50% via early partnership with suppliers and Cisco engineering teams.
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Hardware EngineerComit Systems, Inc 2011 - 2012Design and verification of digital ASICS including DFT insertion and verification. Partnered with customers to understand requirements and co-ordinate design and verification efforts, spanning Comit and customer sites. -
Component Design EngineerIntel Corporation 2009 - 2010Hillsboro, Oregon, United StatesAs one of two people chosen by Intel from Master of Science program at University of Florida, brought in as part of a seven-person team to write tools and automate workflow created to support the on-time delivery of cutting-edge technologies. Collaborated cross-functionally on process roadmap with process and circuit engineers.IMPACTPerformed device parameter extraction for creating Process Design Kit (PDK) using Intel’s proprietary compact models for 32nm node. Designed and maintained tools for model-data validation and developed a fully automated test bench optimizing turn-around time for fine tuning process and device parameters. Boosted team productivity by 30%. -
Software EngineerLsi Logic 2006 - 2007Designed and developed UI controllers for set top boxes. Developed brand new feature for “time shift buffering” or live pause showcased at CES (Consumer Electronics Show). Technology acquired semiconductor.
Ramya Shankar Education Details
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Electrical Engineering -
Electrical, Electronics And Communications Engineering
Frequently Asked Questions about Ramya Shankar
What company does Ramya Shankar work for?
Ramya Shankar works for Cspeed Inc
What is Ramya Shankar's role at the current company?
Ramya Shankar's current role is Product @ cspeed.
What schools did Ramya Shankar attend?
Ramya Shankar attended University Of Florida, Visvesvaraya Technological University.
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4hotmail.com, ibm.com, ibm.com, ibm.com -
Ramya Shankar
Palo Alto, Ca3mdsol.com, gmail.com, medidatasolutions.com1 +141576XXXXX
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