Shekar Siddachar Email & Phone Number

EXPERIENCE SUMMARY• Total 20+ years of experience on ASIC/FPGA Frontend Digital Design & Verification. AREAS OF EXPERTISE • ASIC/FPGA/SoC/IP Verification using SV & OVM methodology.• Test Benches, test cases, OVM components & Behavioral models development using System Verilog/Verilog/VHDL/assembly & C. • Assertions & Coverage development using System Verilog.• RTL development with Verilog & VHDL.• Synthesis & Timing Analysis.• Functional & Gate Level Simulation. • FPGA Board Testing & Layout Design.• Project management and Team leading. TECHNICAL SKILLSLanguages: System Verilog, Verilog, VHDL, C & Assembly 8051Verification Methodology: OVMOS worked with: Unix, Linux [Red Hat], WindowsSynthesis Tools : Design Compiler, Sinplify-pro, Leonardo Spectrum Simulation Tools : DVE, ModelSim, QuestaSim, NcSIM, SimVision, VCSIHardware Debugging Tools : Logic Analyzer, OscilloscopeFPGA Tools : XILINX ISE, Foundation Series, ChipScope, Coregen.ALTERA QUARTUS-II, MAX Plus II, SignalTap, Megawizard, Nios-II IDE 9.0, SOPC builder 9.0.PCB Design Tools : CAD STAR, ORCADDomain/Protocols knowledge : AXI, USB2.0, PCI 2.1, PIF3.0, OCP2.0, I2C, SPI, UART, JTAG, LTE, FlexRay2.1, Micro Controller, NAND Flash.Scripting Language : PERL

Listed skills include Asic/Fpga/Soc/Ip Verification Using Sv And Ovm Methodology, Assertions And Coverage Development Using System Verilog, Rtl Development With Verilog And Vhdl, Synthesis And Timing Analysis, and 5 others.

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  Sri Jayachamaranjendra Collage Of Engg, University Of Mysore

  E&C