Sheril Esther Email & Phone Number

I have 2.5 years experience in RTL design, starting as a Graduate Engineering, then progressed to an Associate Design Engineer as a RTL Design Engineer, where I contributed to the design and verification of several complex and critical systems for aircraft and avionics.Adept in utilizing tools like:1.Xilinx ISE2.Altera Quartus3.Xilinx VivadoStrong knowledge of hardware description language like : Verilog and VhdlImmense capabilities to: Complete RTL coding and verification.Knowledge of SOC architecture.chip level pin planning.FPGAs : Spartan 6, Max10, Zynq7000.Experienced in board level testing and debugging.Modelsim altera, Isim, Logic Analyzer and Virtual input output(VIO).Experience by using constraints to achieve timing requirement.Knowledge in various protocols like SPI, UART Ethernet. Hands on experience with FPGA debugging tools and test & measurement instruments such as oscilloscope and Logic port and strong problem solving and debugging skills.

• 

  Associate Engineer

  Rangsons Aerospace Pvt Ltd

  Aug 2022 - Present - Bengaluru, Karnataka, India

• 

  Kings Engineering College

  Electronics And Communication Engineering