A Senior Silicon Validation Engineer and ATE characterisation with comprehensive expertise in SOC device validation, test program development, and optimization on the Advantest V93k platform. Skilled across wafer sort, final testing, and qualification (HTOL, ESD), including RMA analysis and debugs with a focus on DIB hardware verification, ATE-level test case development, test program integration, test methods and vector validation. Proven leader in cross-functional collaboration for yield improvement, test time reduction, and production efficiency. Adapt in overseeing hardware setups and multisite deployments, managing program version control, and mentoring teams in debugging and project readiness. Proficient in handling escalations, support ad-hoc requests, pilot project deployment, and mentorship in development, debugging, and project readiness.