Please complete the CAPTCHA to continue
@infineon.com
✓
LinkedIn matched
A concise factual answer block for searchers comparing this professional profile.
Shiju Abraham is listed as Physical Design Engineer, Infineon Technologies at Infineon Technologies, based in United States, United States, United States. AeroLeads shows a work email signal at infineon.com and a matched LinkedIn profile for Shiju Abraham.
Shiju Abraham previously worked as Principal Electrical Design Engineer at Infineon Technologies and Senior Staff Electrical Design Engineer at Infineon Technologies. Shiju Abraham holds Master Of Science (Ms), Electrical And Electronics Engineering from The University Of Texas At Arlington.
This section adds company-level context without repeating Shiju Abraham's masked contact details.
AeroLeads found 1 current-domain work email signal for Shiju Abraham. Compare company email patterns before reaching out.
Professional:------------------- Owner for Power/EMIR signoff at SoC level. Work with Floorplan, PnR owners to get the power grid to meet signoff threshold. Have successfully taped out multiple, complex SoCs.- Collaborate with block/IP owners for EMIR signoff, power gird improvement at IP-level. - Experience with power, IR, EM, ramp-up, clock-jitter, ESD analysis with planar CMOS and FDSOI designs. Have worked on blocks with ~2GHz speed and also on low-power SoCs with several power domains. - Pre-layout constraint development and Logic Synthesis for SubSystem, chip-level to help achieve PPA targets.- Owner for DFT timing constraints and STA signoff for DFT modes.- Drive early power optimization/power saving based on RTL-level power analysis using SpyGlass. Work with architects, and logic designers to understand power requirements and find opportunities to reduce power.- Report power for blocks/SubSystems and top-level using RTL-level and gate-level design and corresponding signoff tools. This is for datasheet purpose as well as for regulator sizing. Have done gate-level power reporting using RedHawk and PTPX.- Provide power projection for the future projects based on analysis, find out scaling factors between RTL, gate and Silicon. - RedHawk physical and electrical modeling of Power Switches, LDOs, other IPs- CMM generation using aplmmx/Totem, Power Noise (simultaneous switching noise) analysis using Totem.- Co-design experience. IO/Bump placement, RDL routing.- IOSTA for a few interfaces (25MHz - 133MHz).- Worked on different aspects of Physical Design(Floor Plan, Power Plan, PnR, PV) for 2 successful ASICs in 55nm technology (netlist to GDSII).- Worked on Library development for Standard Cell/IO Cells and IBIS Modeling.- Experience with spice-level simulations. - Comfortable with scripting using tcl, perl, shell.Academic:---------------- MS-Thesis : Developed one of the most compact (layout area) GPIOs in 28nm technology and developed an EDA tool ("IO Planner") which help the user to plan the IO ring suitably by suggesting optimum placement for ESD clamps in the IO ring. Advisor: Dr. Alan W Davis.Goals:---------- Explore different aspects of physical design.
Listed skills include Vlsi, Asic, Perl, Spice, and 27 others.
Company context helps verify the profile and gives searchers a useful next step.
A career timeline built from the work history available for this profile.
Neubiberg, München, DE
- Synthesis, Constraints, and STA for DFT modes- Power Estimation and gate-level power analysis - Power Integrity (EMIR) analyses- Ramp-up/In-rush current analysis- Power Noise/SSN analysis- Collaborate with various teams including, - System architecture, Power architecture, DFT, UPF, FP/PnR, Packaging, CAD, IP, EDA vendors etc.- Mentor junior members in.
Neubiberg, München, DE
Responsible for: - Synthesis for a multi-million, sub-GHz microcontroller (SubSystem + Top-level). Major tasks are: > Constraint debug, constraint update as needed. Timing debug. > Custom updates to the synthesis flow as needed for the project. > Goal is to produce best QoR netlist while collaborating with UPF, DFT owners and other stakeholders from.
Eindhoven, Noord-Brabant, NL
- Drive early power optimization/power saving based on RTL-level power analysis using SpyGlass. Work with architects, and logic designers to understand power requirements and find opportunities to reduce power.- Report power for blocks/SubSystems and top-level using RTL-level and gate-level design and corresponding signoff tools. This is for datasheet.
Eindhoven, Noord-Brabant, NL
- Back-end engineer for ARM based MPU design(s).- Synthesis engineer for a low-power SoC.- Perform Static/Dynamic IR Drop Analysis for FDSOI designs. Both vectorless and VCD based.- Perform Ramp-up (lowpower) analysis for blocks/SubSystems and find out the best way to meet the ramp-up threshold.- Run Power EM, Signal EM and ESD checks using RedHawk.- RTL.
Eindhoven, Noord-Brabant, NL
- Back-end engineer for ARM based MPU design(s).- Synthesis engineer for a low-power SoC.- Perform Static/Dynamic IR Drop Analysis for FDSOI designs. Both vectorless and VCD based.- Perform Ramp-up (lowpower) analysis for blocks/SubSystems and find out the best way to meet the ramp-up threshold.- Run Power EM, Signal EM and ESD checks using RedHawk.- RTL.
Eindhoven, Noord-Brabant, NL
- Back-end engineer for ARM based MPU design(s).- Synthesis engineer for a low-power SoC.- Perform Static/Dynamic IR Drop Analysis for FDSOI designs. Both vectorless and VCD based.- Perform Ramp-up (lowpower) analysis for blocks/SubSystems and find out the best way to meet the ramp-up threshold.- Run Power EM, Signal EM and ESD checks using RedHawk.- RTL.
Eindhoven, Noord-Brabant, NL
(Joined Freescale Inc. and it was acquired by NXP in December-2015)- Back-end engineer for ARM based MPU design(s).- Synthesis engineer for a low-power SoC.- Co-design Engineer. Work with the Architect/block owners, integration/ESD engineers and packaging team to define the IO Cell placement, IO integration, bump placement etc to come up with the IOPLAN.
Arlington, TX, US
Graduated with MS (Thesis) in Electrical Engineering
Malta, NY, US
Worked on developing an I/O ring, RC clamp characterization and ESD network analysis.
Bangalore, Karnataka, IN
Worked on netlist to GDSII implementations in 55nm.
Bangalore, Karnataka, IN
IBIS modeling and Automation/EDA development.
Bangalore, Karnataka, IN
Worked in STD/IO cell characterization, STD cell layout and IBIS modeling.
Cambridge, Cambs, GB
[This assignment was done when I worked as "Project Engineer" with Wipro Technologies]- Worked on generating STD CELL libraries and EDA views for technology nodes from 130nm to 40nm.- Worked on client-site and along with client engineers.
Quick answers generated from the profile data available on this page.
Shiju Abraham works for Infineon Technologies.
Shiju Abraham is listed as Physical Design Engineer, Infineon Technologies at Infineon Technologies.
AeroLeads has found 1 work email signal at @infineon.com for Shiju Abraham at Infineon Technologies.
Shiju Abraham is based in United States, United States, United States while working with Infineon Technologies.
Shiju Abraham has worked for Infineon Technologies, Nxp Semiconductors, University Of Texas At Arlington, Globalfoundries, and Wipro Technologies.
You can use AeroLeads to view verified contact signals for Shiju Abraham at Infineon Technologies, including work email, phone, and LinkedIn data when available.
Shiju Abraham holds Master Of Science (Ms), Electrical And Electronics Engineering from The University Of Texas At Arlington.
Shiju Abraham is listed with skills including Vlsi, Asic, Perl, Spice, Physical Design, Cmos, Circuit Design, and Integrated Circuit Design.
Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.
Start free trial Search contacts