It was a journey from setbacks to expertise, where each twist shaped a story of resilience and passion. 🚀💡 From the streets of Kanpur, UP - India, my technology journey started with setbacks - I couldn't crack the JEE Mains or AIEEE entrance exams for IIT or NIT admission. Undeterred, the second attempt at the state-level engineering entrance exam led me to Kanpur University (CSJMU) for a BTech in Electronics and Communication Engineering.In my final year, an opportunity in Bangalore's semiconductor hub slipped through due to ignorance, redirecting me to the telecom industry. Realization struck after a year; VLSI and semiconductors were my calling. Securing interviews in Bangalore, I finally landed a job in the same company that eluded me earlier.Venturing into VLSI full custom and standard cell layout design, I embraced challenges in cutting-edge technologies, I craved more challenges. Seeking more, I transitioned to the Physical Design domain by undergoing training in a VLSI institute in Bangalore and hands-on experience during that time, laid the foundation for becoming a testchip pd engineer.Current Endeavours:Educational pursuits beckoned, leading me to pursue MTech in Microelectronics while contributing as a Senior Physical Design Engineer at Synopsys. Silicon Validation is my realm in my current role - I conduct PnR implementation and verification checks for logic library test chips. With 8 years of cumulative experience in the semiconductor industry, my skills span Block level PnR implementation, Silicon Validation, Manually fixing DRC at chip-top level, managing PV checks (DRC, LVS, ERC, ANTENNA), Formality, Extraction, EM, and IR analysis, I’ve worked on fixing STA constraint requirements, max transition and max cap violation fixing for the test chip projects. I have expertise in VLSI layout design as well. And maintaining QMS documentation for test chip projects underscores my commitment to precision. Here I got a chance to work on different technologies and foundries such as - Intel 18A, Samsung 4nm and 8nm, TSMC N3P, N3E, N5 auto-grade and Global Foundry GF22FDX_Plus node.Beyond professional endeavours, I'm passionate about sharing knowledge. I'm eager to share my technical insights and knowledge with those seeking expertise in TCL scripting or Physical Design.