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Shivanand Ramesh Pujari Email & Phone Number

NVIDIA | USC | Stanford at NVIDIA
Location: San Francisco Bay Area, United States, United States 8 work roles 4 schools
1 work email found @nvidia.com LinkedIn matched
✓ Verified May 2026 4 data sources Profile completeness 100%

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Work email s****@nvidia.com
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Current company
NVIDIA
Role
NVIDIA | USC | Stanford
Location
San Francisco Bay Area, United States, United States

Who is Shivanand Ramesh Pujari? Overview

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Quick answer

Shivanand Ramesh Pujari is listed as NVIDIA | USC | Stanford at NVIDIA, based in San Francisco Bay Area, United States, United States. AeroLeads shows a work email signal at nvidia.com and a matched LinkedIn profile for Shivanand Ramesh Pujari.

Shivanand Ramesh Pujari previously worked as Senior Physical Design Engineer at Nvidia and Intern at Nvidia. Shivanand Ramesh Pujari holds Scpd, Ai from Stanford University.

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Email format at NVIDIA

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{first_initial}{last}@nvidia.com
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AeroLeads found 1 current-domain work email signal for Shivanand Ramesh Pujari. Compare company email patterns before reaching out.

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Profile bio

About Shivanand Ramesh Pujari

8 years of experience in Physical Design (RTL-GDSII), worked on 5nm,7nm,14nm,16nm,28nm, 180nm technology RTL- GDSII implementation. Proficient in APR, Signoff STA, DFM, EM/IR analysis, X-talk, noise analysis and timing/functional ECO implementation. • EDA Tools: IC Compiler, Conformal, Calibre, SoC Encounter/Innovus, Virtuoso, StarRC, PrimeTime, ModelSim, QuestaSim, Design Compiler and RC Compiler/Genus, Apache RedHawk.• Programming languages: C, C++, Verilog, System Verilog, PERL, Python, TCL, Shell scripting.

Listed skills include Verilog, Asic, Static Timing Analysis, Physical Design, and 47 others.

Current workplace

Shivanand Ramesh Pujari's current company

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NVIDIA
Nvidia
NVIDIA | USC | Stanford
Santa Clara, CA
Website
nvidia.com
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8 roles

Shivanand Ramesh Pujari work experience

A career timeline built from the work history available for this profile.

Senior Physical Design Engineer

Current
Nvidia

Santa Clara, CA, US

Baking GPUs

Jul 2019 - Present

Intern

Nvidia

Santa Clara, CA, US

Jan 2019 - May 2019

Research Assistant

Usc Viterbi School Of Engineering

Los Angeles, California, US

Working with Prof. Peter Bereel for low power, side channel resistant Asynchronous design research group.Working on constraint and methodology development for Async architectures.

Aug 2018 - Dec 2018

Intern

Mediatek

Hsin-Chu, TW

Worked with the Advanced CPU team for performance improvement.

May 2018 - Aug 2018

Design Engineer Ii (Rtl-Gdsii)

Appliedmicro

Santa Clara, CA, US

  • RTL to GDS implementation of Load Store Unit and Memory Management Unit of CPU core for industries first ARM64 bit server class processor and optimizing the implementations for power, timing and area.
Jun 2014 - Jul 2017

Ice Physical Design Engineer

Intel Corporation

Santa Clara, California, US

Mar 2014 - Jun 2014

Trainee Engineer

Rv-Vlsi Design Center

Jayanagar 4th T Block, Karnataka, IN

Here I have gained relevant experience in VLSI Physical Design in & gained exposure to industry standard EDA tools.

Jul 2013 - Jan 2014
Team & coworkers

Colleagues at NVIDIA

Other employees you can reach at nvidia.com. View company contacts →

AP Aleksei Prokopenko Aleksei Prokopenko Colleague at Nvidia United States, United States View → JY Jonathan Yang Jonathan Yang Colleague at Nvidia Palo Alto, California, United States, United States View → JE Jessica Eckford Jessica Eckford Colleague at Nvidia Santa Cruz, California, United States, United States View → MG Michael Garrett Michael Garrett Colleague at Nvidia Greater Boston, United States, United States View → LS Lino Sabia Lino Sabia Colleague at Nvidia Fano, Marches, Italy, Italy View → MM Meta Mckinney, Mlis Meta Mckinney, Mlis Colleague at Nvidia Greater Madison Area, United States, United States View → AM Austin Martin Austin Martin Colleague at Nvidia United States, United States View → SD Sarah D. Sarah D. Colleague at Nvidia Greater Colorado Springs Area, United States View → RL Rob Likovich Rob Likovich Colleague at Nvidia Wake Forest, North Carolina, United States, United States View → 段 段宇华 段宇华 Colleague at Nvidia Singapore, Singapore, Singapore View →
4 education records

Shivanand Ramesh Pujari education

Scpd, Ai

Stanford University

Master Of Science, Electrical Engineering

University Of Southern California

Master Of Science - Ms, Business Administration And Management, General

University Of Illinois Urbana-Champaign

Bachelor Of Engineering (Be), Electronics And Communication Engineering

Visvesvaraya Technological University
FAQ

Frequently asked questions about Shivanand Ramesh Pujari

Quick answers generated from the profile data available on this page.

What company does Shivanand Ramesh Pujari work for?

Shivanand Ramesh Pujari works for NVIDIA.

What is Shivanand Ramesh Pujari's role at NVIDIA?

Shivanand Ramesh Pujari is listed as NVIDIA | USC | Stanford at NVIDIA.

What is Shivanand Ramesh Pujari's email address?

AeroLeads has found 1 work email signal at @nvidia.com for Shivanand Ramesh Pujari at NVIDIA.

Where is Shivanand Ramesh Pujari based?

Shivanand Ramesh Pujari is based in San Francisco Bay Area, United States, United States while working with NVIDIA.

What companies has Shivanand Ramesh Pujari worked for?

Shivanand Ramesh Pujari has worked for Nvidia, University Of Southern California, Usc Viterbi School Of Engineering, Mediatek, and Appliedmicro.

Who are Shivanand Ramesh Pujari's colleagues at NVIDIA?

Shivanand Ramesh Pujari's colleagues at NVIDIA include Aleksei Prokopenko, Jonathan Yang, Jessica Eckford, Michael Garrett, and Lino Sabia.

How can I contact Shivanand Ramesh Pujari?

You can use AeroLeads to view verified contact signals for Shivanand Ramesh Pujari at NVIDIA, including work email, phone, and LinkedIn data when available.

What schools did Shivanand Ramesh Pujari attend?

Shivanand Ramesh Pujari holds Scpd, Ai from Stanford University.

What skills is Shivanand Ramesh Pujari known for?

Shivanand Ramesh Pujari is listed with skills including Verilog, Asic, Static Timing Analysis, Physical Design, Tcl, Cmos, Vlsi, and C.

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