o Performed verification of a RAM controller for Intel QuickAssist™ Technology using OVM, System Verilog and Intel-specific methodologies. o Created coverage driven constraint random verification environment including sequences, tests, interface checkers, IP protocol checks and configurable test bench using System Verilog and OVM.o Created configurable test benches to support verification of multiple flavors of accelerator IP to enable simultaneous tape out of various products.o Developed and maintained detailed verification test plan for all features in RAM controller including stimulus, checking and functional coverage plans. o Defined and implemented functional coverage, analyzed holes in the coverage, randomized existing tests, and developed directed tests to ensure coverage closure.

Design FPGAs for Big Data Acceleration, Analytics and Warehouse appliances- Developed, simulated, synthesized, verified, and documented code for FPGA/ASIC using Verilog. - Developed unit Testbench for design modules to verify the code functionality.- Explored Altera/Xilinx OpenCL FPGA compiler performance using different algorithms like LZW, LZ77, string matching and dictionary search'Functional Verification of FPGA and Bringup for ASIC-Debugged and characterized LBIST for the bringup ASIC team. -FPGA verification using IBM internal tools “Fusion” to increase system reliability. Task included documentation, tracking, escalation of issues and fixing software bugs.

• Low power dynamic energy prediction scheme (Manuscript to be submitted) -Developed an adaptive energy prediction algorithm AFP using forward prediction filter technique with high accuracy and low computational overhead.• Adaptive energy management algorithm for real-time energy harvesting systems -Developed an initial energy management scheme using EWMA prediction algorithm -Dynamically adjusting the schedule based on the error in energy prediction during runtime • Strategized and supervised senior year students final project-“Underwater Microbial Fuel Cell Design and Implementation”