Shravanthi Reddy work email
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Shravanthi Reddy personal email
Summary:~Experienced in RTL design, Functional verification of IP, Test plan development, Coverage analysis, Testcase development (Directed and Random) and Assertions.~Graduated from University of Texas at Dallas with major in Electrical Engineering.~My course work includes Advance Digital Logic, VLSI Design, Computer Architecture, Testing of Digital Systems,Applications of Data Analytics in Semiconductor manufacturing, Microprocessor SystemsSkill set:Languages: System Verilog, Verilog, CScripting Languages: Python, ShellMethodologies: UVMProtocols: AMBA AXI, AHB, APB, DDR(DDR4 and DDR5)Synthesis Tools: Synopsys Design Compiler, Xilinx ISECadence Tool Suite: Cadence Virtuoso, Incisive, Xcelium,Cadence Schematic Editor, EDI EncounterSynopsys Tool Suite: VCS, Verdi, Tetramax, Library Compiler, PrimeTime, SiliconSmart, HSPICE, WaveView Testing: Memory Testing, Design For Test, Scan, BISTInterests: RTL Design & Verification, Logic Design, Computer Architecture.
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Design Verification EngineerAmazon Web Services (Aws) Jun 2022 - PresentSeattle, Wa, Us
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Asic Digital Design Engineer Sr ISynopsys Inc Dec 2021 - Jul 2022Sunnyvale, California, Us -
Asic Digital Design Engineer IiSynopsys Inc Apr 2019 - Dec 2021Sunnyvale, California, Us-Responsible for Test plan and testcase development for DDR5 based BIST Controller.-Collaborate with Verification and Design Engineers to create and review test plans and resolve the bugs.-Run weekly regressions, debug testbench and RTL bugs, analyze code and functional coverage to identify uncovered scenarios.- Add exclusions to improve the coverage.
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Asic EngineerMarvell Semiconductor Sep 2018 - Mar 2019Santa Clara, Ca, Us• Knowledge of DDR3,DDR4,DDR5.• Developed simulation flow for Memory Controller in Xcelium (Cadence) Platform.• Involved in running test regressions and debugging functional failures. -
Asic Design InternMarvell Semiconductor Jul 2017 - Dec 2017Santa Clara, Ca, Us• Developed scripts to automate register value calculations in the Memory Controller design for different Memory architectures.• Run regressions to verify functionality by performing functional coverage analysis. Analyzed the failures to determine if it is a design or test bench issue.• Based on design,architecture and updated RTL features, developed a verification plan to provide functional coverage for the design.• Generated and simulated test cases and developed a Perl script to compute the coverage of regression model.
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Project InternSouth Central Railway Workshop,India Jan 2016 - Apr 2016Designed and developed an embedded system to automate the process of testing of railway wagon within brake testing division.Hardware used: Arduino Mega 2560, Pressure sensors, TFT LCD.
Shravanthi Reddy Skills
Shravanthi Reddy Education Details
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The University Of Texas At DallasElectrical Engineering -
Chaitanya Bharathi Institute Of TechnologyElectronics And Communication Engineering
Frequently Asked Questions about Shravanthi Reddy
What company does Shravanthi Reddy work for?
Shravanthi Reddy works for Amazon Web Services (Aws)
What is Shravanthi Reddy's role at the current company?
Shravanthi Reddy's current role is Design Verification Engineer.
What is Shravanthi Reddy's email address?
Shravanthi Reddy's email address is sh****@****sys.com
What schools did Shravanthi Reddy attend?
Shravanthi Reddy attended The University Of Texas At Dallas, Chaitanya Bharathi Institute Of Technology.
What are some of Shravanthi Reddy's interests?
Shravanthi Reddy has interest in Children, Environment, Education, Poverty Alleviation, Science And Technology, Disaster And Humanitarian Relief, Arts And Culture, Health.
What skills is Shravanthi Reddy known for?
Shravanthi Reddy has skills like C, Verilog, Vlsi, Python, Microprocessors, Xilinx Ise, Assembly Language, Computer Architecture, System Verilog, Synopsys Tools, Synopsys Primetime, Cadence Encounter.
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