Shrinath Madinur Email & Phone Number

In the past I have been involved with Network Chip Development in the following areas:Architecture, Micro-architecture, Emulation and Validation Planning, Synthesis, RTL Coding, Gate Level Simulations, Functional Verification, Static Timing Analysis and Timing closureI have spent the last few years focusing on FPGA Emulation , FPGA Test Environment Creation and Post Silicon Validation targeted towards Ethernet and OTN Chips and Products. Responsible to develop Architecture and Micro-Architecture of a blocks in a chip, Write RTL Design Code, Integration of some pre verified IP's, Perform Synthesis, Gate Level Simulations, Interaction with various teams/ IP Vendors.Specialties: Front end RTL CodingFPGA Back endFunctional VerificationLogic Synthesis,Static Time Analysis and Timing Closure.FPGA Emulation and PrototypingSystem Bring up Hardware Emulation using ToolsPost Silicon ValidationLanguages Specialties: Verilog, SystemVerilog,VHDL,Python, C, Tcl.