Shreya Gupta Email and Phone Number
Shreya Gupta personal email
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"7+ years of industry experience in RTL logic design, synthesis, simulation, and verification. Currently working as ASIC Digital Design Engineer at Apple, designing digital blocks for mixed-signal circuits such as ADC/DAC, using Verilog/System Verilog as well as running standard quality checks like Lint, CDC, RDC, Jasper sanity. Experience in defining constraints for various clock/modes, creating test-benches to debug complex logic simulations, and developing silicon firmware using C programming on ARM M3 CPUs. Exposure to APB/AHB bus architecture, as well as custom circuit design and validation for memory designs. My mission is to deliver high-quality, innovative, and reliable solutions for the products and customers of an organization"
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Asic Digital Design EngineerApple Aug 2019 - PresentCupertino, California, Us• Design digital blocks with latest industry tools in mixed signal circuits such as ADC/DAC. • Responsibilities include defining Micro-Architecture spec and implementing Digital Design using verilog/system verilog and running standard quality checks like Lint, CDC, RDC, Jasper sanity. • Experience in defining constraints for various clock/modes and creating testbenches to debug complex logic simulations. • Experience with APB/AHB bus architecture and C/C++ firmware development for ARM M3 CPUs• Experience creating automation scripts with python and TCL.
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Analog/Mixed Signal Design EngineerIntel Corporation Oct 2017 - Aug 2019Santa Clara, California, UsMember of the Non-Volatile Memory Solutions Group (NSG) working on 3D NAND memory products. Responsibilities include but are not limited to: Static Timing Analysis, RTL design, synthesis and APR, custom circuit design and validation, top level analog system design and integration, intensive analog and mixed-signal validation and debug across PVT. -
Mixed Signal Pre Silicon Verification Graduate InternIntel Corporation Jan 2017 - Jul 2017Santa Clara, California, UsResponsible for RTL design and verification of logic and circuits for 3D NAND memory designs in Intel’s Non-Volatile Memory Group.
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Memory Design And Verification InternGlobalfoundries May 2016 - Aug 2016Malta, Ny, UsKey Role and Responsibilties :-Verified using System Verilog the logic of different functions/configurations of a memory product as mentioned in the verification checklist(achieved the July end deadline) by setting up the testbenches, netlisting schematics and tasks/pattern generation.-Suggested a design change in the FAILCOUNT determination for the memory product which reduced the number of transistors by 50% approximately.-Updated the existing Perl scripts from time to time to make verification process more efficient. -Worked on the transient verification of the cross section of the memory product using Cadence Design Suite and NC Verilog.-Worked on the documentation for the memory product’s Test site. -
Graduate Teaching AssistantPenn State University Jan 2016 - May 2016University Park, Pa, UsTeaching Assistant for CMPSC 203 (Introduction to Spreadsheets and Databases) . Worked in the capability of course development assistant, Lab TA, and grader . -
StudentDelhi College Of Engineering Aug 2014 - May 2015Delhi, Delhi, Ino Implementation of vedic multipliers in MOS current mode logic (MCML) style. o Two architectures for MCML Vedic multipliers were simulted in PSpice using TSMC 0.18um CMOS process technology.o The first one is based on Urdhva Tiryagbhyam Sutra of Vedic mathematics whereas the second one modifies the blocks used in the first one to reduce the computations.
Shreya Gupta Skills
Shreya Gupta Education Details
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Penn State UniversityElectrical Engineering -
Delhi Technological University (Formerly Dce)Electrical And Electronics Engineering
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Kendriya Vidyalaya Shalimar Bagh
Frequently Asked Questions about Shreya Gupta
What company does Shreya Gupta work for?
Shreya Gupta works for Apple
What is Shreya Gupta's role at the current company?
Shreya Gupta's current role is ASIC Digital Design Engineer @ Apple | Digital Design.
What is Shreya Gupta's email address?
Shreya Gupta's email address is sh****@****ail.com
What schools did Shreya Gupta attend?
Shreya Gupta attended Penn State University, Delhi Technological University (Formerly Dce), Kendriya Vidyalaya Shalimar Bagh.
What are some of Shreya Gupta's interests?
Shreya Gupta has interest in Social Services, Economic Empowerment, Civil Rights And Social Action, Environment, Poverty Alleviation, Science And Technology, Human Rights, Animal Welfare, Arts And Culture, Health.
What skills is Shreya Gupta known for?
Shreya Gupta has skills like Fpga, Pspice, Verilog Hdl, Digital Circuit Design, C, C++, Simplescalar, Matlab, Analog Circuit Design, Computer Architecture, Microsoft Excel, Microsoft Office.
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