Shreya Gupta Email & Phone Number

Cupertino, California, Us

• Design digital blocks with latest industry tools in mixed signal circuits such as ADC/DAC. • Responsibilities include defining Micro-Architecture spec and implementing Digital Design using verilog/system verilog and running standard quality checks like Lint, CDC, RDC, Jasper sanity. • Experience in defining constraints for various clock/modes and creating testbenches to debug complex logic simulations. • Experience with APB/AHB bus architecture and C/C++ firmware development for ARM M3 CPUs• Experience creating automation scripts with python and TCL.

Santa Clara, California, Us

Member of the Non-Volatile Memory Solutions Group (NSG) working on 3D NAND memory products. Responsibilities include but are not limited to: Static Timing Analysis, RTL design, synthesis and APR, custom circuit design and validation, top level analog system design and integration, intensive analog and mixed-signal validation and debug across PVT.

Santa Clara, California, Us

Responsible for RTL design and verification of logic and circuits for 3D NAND memory designs in Intel’s Non-Volatile Memory Group.

Malta, Ny, Us

Key Role and Responsibilties :-Verified using System Verilog the logic of different functions/configurations of a memory product as mentioned in the verification checklist(achieved the July end deadline) by setting up the testbenches, netlisting schematics and tasks/pattern generation.-Suggested a design change in the FAILCOUNT determination for the memory product which reduced the number of transistors by 50% approximately.-Updated the existing Perl scripts from time to time to make verification process more efficient. -Worked on the transient verification of the cross section of the memory product using Cadence Design Suite and NC Verilog.-Worked on the documentation for the memory product’s Test site.

University Park, Pa, Us

Teaching Assistant for CMPSC 203 (Introduction to Spreadsheets and Databases) . Worked in the capability of course development assistant, Lab TA, and grader .

Delhi, Delhi, In

o Implementation of vedic multipliers in MOS current mode logic (MCML) style. o Two architectures for MCML Vedic multipliers were simulted in PSpice using TSMC 0.18um CMOS process technology.o The first one is based on Urdhva Tiryagbhyam Sutra of Vedic mathematics whereas the second one modifies the blocks used in the first one to reduce the computations.

Master Of Science (M.S.), Electrical Engineering

Bachelor Of Technology (Btech), Electrical And Electronics Engineering

Education record