Responsible for Architecture of Ethernet switch ingress and egress packet processing pipeline. Architected Global policer, Global traffic manager, Stats, and INT module. Responsible for Architecture of Memory subsystem in Next Gen SmartNICPerformance analysis of BW and Latency with a variety of workloads for networking & compute clients to the Memory subsystemLed the CXL use case working group across the organization, define documented, future-looking CXL use cases.

RISCV processor & infrastructure implementation in FPGA

Cloud FPGA Architect (Data Center Group)Played critical role in AWS F1 design win - Architect the productPlayed critical role in other T-1 FAAS design, architect of the security features in the VU9P based boardTechnical lead on China based Data base accelerator, critical role played in integration in their environmentTechnical lead on T-1 FPGA accelerator (Compression, security, de-duplication, erasure code, RSA2K/4K, IPSec, ECDH and ECDSA) in big data serversTechnical lead and provided guidance to internal team on NVMEoF implementation and presented to multiple storage customersRepresented Xilinx on Ethernet Alliance, COBO, ONF, SNIA, N-BASE-T allianceInternally drove Virtio driver development for customer in chinaArchitect & provide guidance on use of FPGA in various storage platforms for customersArchitect & Development of various accelerators for big data servers, storage systemsWrote specification of firmware development for VU9P based board in OEM, Hyperscale customers environment.Chip Architect : T-1 customer in security platform based on FPGAArchitect of hybrid cloud solutions with Equinix and AWS/Azure/GCP.

Chief Systems Architect at PLX to push MR-IOV based solutions in the market.

Architecture Team.

Chip Architect

System Architect and Chip designerChip Design Responsibility: Micro Architect and implementation of the Flow control unit in a single stage, three-stage Clos fabric. Architecture and implemented SerDes interfaces to the core logicArchitected the system-level solutionsWon a company's lifesaver award to contribute to a unique single stage architecture to reduce the number of chips required to implement a terabit/sec fabric

Lead ASIC designer and HW Architect