Vatsa Prahallada work email
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Automotive & Automation - [Current: Technical Director]- Developing next-generation SoC integration platform for scalability and cost-sensitive derivatives.- Handle post-silicon engineering tools, flows, and methodologies that include diagnostics infrastructure.- Provide tooling and manage Functional Safety for design enablement.- Co-chairing companywide Traceability TFM board and member of the Accellera FuSa committee. - Knowledgeable in RISC-V architecture.Public Git: https://github.com/vatsamailAutomotive CAD - Functional Safety [Past]- Operate as Global Automotive Hardware CAD Lead - ISO26262 certified- Interface b/w software, systems, and Safety domainsEDA Operations [Past]- A member of the EDA operations team that is responsible for managing EDA infrastructure across the company. - With a proven track record of saving millions of dollars by strategically migrating to different EDA tool vendors. - Responsible for forecasting multi-million dollar EDA budgets by using statistical models, engineering forecasts, and product roadmaps. - With strong engagement with the vendors, engineering domain experts, and management, the team operates by optimizing, scheduling, and predicting nonrecurring engineering costs.- An automation evangelist methodically deploying production-worthy solutions using various Python-based frameworks [Django, Numpy, Pandas, Keras] on a platform composed of MySQL, Jenkins, and Perforce using Kanban methodology. DFT Diagnostics tool developer [Past] - Led the high-volume diagnostics tool development team. Conceived-Constructed-Implemented-Deployed-Trained many in-house tools and methodologies. Closely worked with pre-silicon DFT and simulation engineers, Test and product engineers, IT engineers, and Yield, and Failure analysis engineers to develop innovative solutions in the field of product and test engineering relying on Scrum ideologies.Simulations tool developer [Past] - Started as a simulation tools developer at Qualcomm. Responsible for developing in-house Iddq estimation tools, and pre-silicon cross-domain correlation tools. A developer of the automation suite for conducting silicon debugging and the first-generation tracking and monitoring system. Automation Engineer [Past] - Learning the concepts of VLSI at Intel and co-developing automation solutions for conducting pre-silicon performance verification. Responsible for conducting full-chip timing analysis for Xeon processors. Partnered with the post-silicon engineering team to enhance and co-develop a speed-path debug tool.
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Director Of EngineeringArmPoway, Ca, Us -
Technical DirectorNxp Semiconductors Dec 2021 - PresentEindhoven, Noord-Brabant, Nl* Handling DFT Scan Diagnostics and post-silicon-related tools/flows.* Enabling Functional Safety related tools/flows.* Developing/Architecting in-house infrastructure and automation-related tools.* Representing NXP at IEEE Accellera committees. -
Advisor | Initial InvestorTymeline Jan 2020 - PresentAustin, Texas, UsAs an advisor and an initial investor, I work with the co-founders, on the planning, architecting, and deploying of the product, Tymeline. I enjoy working on conceiving newer features, prototyping, alpha testing and brainstorming about this product with my professional acquaintances.Check out https://tymeline.appTymeline (A product of Quanscendence) is a blockchain-based solution for workforce management. -
Principal EngineerQualcomm Jul 2008 - Dec 2021San Diego, Ca, UsIn this tenure, Vatsa has operated in various roles at different levels.> Lead Global Automotive CAD team - Responsible for delivering FME(D)A, Tool compliance, Traceability, DFT, Longtail, Fault Injection, Implementation, virtual platforms, formal and Static Analysis solutions. As a lead, Vatsa represented the team in various technical and strategic forums that included Safety, Design, DV, PD, DFT, SVE, PTE, and software teams. With ISO26262 certification, he is an active member of the Accellera Committee who has hands-on experience in using Synopsys, Cadence, and Mentor-based automotive tools and flows. Vatsa has actively participated in the end-to-end ASIL B(D) automotive SoC development.> Developed high-volume scan diagnostics solution to ramp up the yield on the advanced nodes. Vatsa has led the flow development effort that worked with DFT, PTE, and Yield tool suites.> Worked in EDA licensing and automation team, primarily responsible for leading licensing portfolios, developing license forecasts, and cost models.> Hands-on experience in developing Test methods, test flows, and test programs with a focus on fuse configuration and ATPG. Prior to that, he has worked as a gate-level simulation engineer and test engineer. -
Senior Component Design EngineerIntel India Jun 2004 - Jul 2008Santa Clara, California, UsBeing part of the hexacore and octa-core Xeon processor tape-outs, gained hands-on experience in Full chip timing analysis (STA), netlist building, speed path debug analysis, Timing spec generators, data monitors development.
Vatsa Prahallada Skills
Vatsa Prahallada Education Details
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Manipal Academy Of Higher EducationAutomations -
Visvesvaraya Technological UniversityComputer Science And Engineering
Frequently Asked Questions about Vatsa Prahallada
What company does Vatsa Prahallada work for?
Vatsa Prahallada works for Arm
What is Vatsa Prahallada's role at the current company?
Vatsa Prahallada's current role is Director of Engineering.
What is Vatsa Prahallada's email address?
Vatsa Prahallada's email address is sp****@****omm.com
What schools did Vatsa Prahallada attend?
Vatsa Prahallada attended Manipal Academy Of Higher Education, Visvesvaraya Technological University.
What skills is Vatsa Prahallada known for?
Vatsa Prahallada has skills like Perl, Eda, Tcl, Vlsi, Verilog, Static Timing Analysis, Asic, C++, Soc, Debugging, Rtl Design, Systemverilog.
Who are Vatsa Prahallada's colleagues?
Vatsa Prahallada's colleagues are Pieter Goossens, Jeroen Caspers, Maik Brett, Kraig Krause, Lisa Bradley, Jérôme Toulouse, Issarapong Wongsuthipakorn.
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