Shruthi Ls Email & Phone Number

Bengaluru, Karnataka, India

Project: Automation for IP view generation• Ensuring correctness of Standard Cell IP/GPIO Libraries by comparing OA and- GDS using LVL, LVS & SVS checks with SKILL and Python• Verifying inhouse flows for Library View generation for Std Cell Ips provided byTSMC for final validation of views generated by checking all the logs generated.• Working on TSMC 2nm, 3nm, 5nm,7nm, technology nodes.• Leading a team of 10 engineers for this activityProject: Automation for extracting… Show more Project: Automation for IP view generation• Ensuring correctness of Standard Cell IP/GPIO Libraries by comparing OA and- GDS using LVL, LVS & SVS checks with SKILL and Python• Verifying inhouse flows for Library View generation for Std Cell Ips provided byTSMC for final validation of views generated by checking all the logs generated.• Working on TSMC 2nm, 3nm, 5nm,7nm, technology nodes.• Leading a team of 10 engineers for this activityProject: Automation for extracting Schematic hierarchical nets and Device Properties• Automated the generation of Excel Sheet report that includes nets information, simulation values and device properties.• Traversing the hierarchy in s schematic for the library provided in the configuration file and get all the pins info of the devices connected in the library using SKILL.• Calculating the drive strength, device flavors, device polarity, device length, width parameters using SKILL.• Wrote a Python wrapper to read the data form the configuration file and fetch the layout and schematic values specified in it.• Earlier it was taking 2 days to generate this report in Excel. With the automation implemented, it takes 3-4 minutes to generate the same report. • Received Certificate of Appreciation form HCLTech for automating the process of Extracting the Device Properties and in achieving higher productivity and helping the team meeting the project deadlines Show less

Bangalore Urban, Karnataka, India

PDK (Process Design Kit) Development:• Developed Physical Verification Design Rule Deck using SVRF (Standard Verification Rule Format) In Assura and PVS.• Working on Physical Verification Layout vs Schematic (LVS) in PVS.• Developed LDMOS PCELLS with CDF and CDF callback using SKILL scripts.• Developed custom SKILL script of metal rectangle creation for fill based on the boundary box selected by the user.EDA Tool Development:Power Device Generator (PDG) – Development… Show more PDK (Process Design Kit) Development:• Developed Physical Verification Design Rule Deck using SVRF (Standard Verification Rule Format) In Assura and PVS.• Working on Physical Verification Layout vs Schematic (LVS) in PVS.• Developed LDMOS PCELLS with CDF and CDF callback using SKILL scripts.• Developed custom SKILL script of metal rectangle creation for fill based on the boundary box selected by the user.EDA Tool Development:Power Device Generator (PDG) – Development of user-friendly tool to generate automated POWERFET layouts in no time.• Pivotal role in development of PDG tool in line with client’s requirements. Used C++ programming in Qt creator integrated with Glade APIs.• Independently developed & integrated various modules viz. Metallization, Via Placement, Metal Slotting, Shorting of Source & Drain metal lines, Sensefet Placement & Connection, Guard ring and Gate Connect.• Implemented a dedicated feature to achieve Tapering of metals. Used complex back-end algorithm to derive non rectilinear shapes.• Worked on core algorithm to implement Bondpad addition/relocation, clearing vias and slots underneath the bond pads.• Integrated PDG with R3D to verify Rdson.• Led a team of 2 during the execution phase of the project. Show less

Bengaluru, Karnataka, India

Analog and Mixed Signal Layout Design:• Worked on various block level projects – Single Stage Amplifier, Resistor Ladder, Capacitor Array and Low dropout regulator.• Hands on experience in area estimation, floorplan & layout implementation of resistor divider network, protection circuits and custom digital circuits.• Well versed with matching of differential pairs, current mirrors, resistor network array, area optimization, minimizing parasitics and routing considering the current… Show more Analog and Mixed Signal Layout Design:• Worked on various block level projects – Single Stage Amplifier, Resistor Ladder, Capacitor Array and Low dropout regulator.• Hands on experience in area estimation, floorplan & layout implementation of resistor divider network, protection circuits and custom digital circuits.• Well versed with matching of differential pairs, current mirrors, resistor network array, area optimization, minimizing parasitics and routing considering the current density.• Actively participated in the layout reviews & carried out necessary modifications/improvements in the layout.• DRC & LVS verification of the blocks using Assura Verification suite.Accomplished following as Trainee Engineer:* Gained comprehensive knowledge of analog layout implementation and verification tools.• Gained good understanding in analog layout requirements such as area optimization, device matching, shielding, minimizing parasitics and guard rings.• Gained good understanding in the issues of Electromigration and IR drop, Antenna effect, Latch up, ESD and advance process effects such as LOD and WPE.• Gained knowledge of circuit functionality of comparators, bandgaps, and amplifiers. Show less

Bengaluru, Karnataka, India

Coaching for High school students in Mathematics, Physics and Chemistry

Bengaluru, Karnataka, India

Development of USB based Data Acquisition System using Actel FPGA• Acquiring the data from the external world with respect to clock to the FPGA through FTDI FT232• Roles and responsibilities: Writing of requirements document, Programming the Kit, Writing Test Benches and bug fixing. Tools : MicrosemiLiberoSoC + Modelsim 10.3c.

Master Of Technology (M.Tech.), Electronics And Communications Engineering

Bachelor'S Degree, Electronics And Communications Engineering