Shruthi Ls
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Shruthi Ls Email & Phone Number

EDA Tool Development | PDK Development | AMS Layout Design | Design Flow Automation | VLSI | Semiconductors | Silicon at HCLTech
Location: Bengaluru, Karnataka, India 5 work roles 2 schools
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Current company
Role
EDA Tool Development | PDK Development | AMS Layout Design | Design Flow Automation | VLSI | Semiconductors | Silicon
Location
Bengaluru, Karnataka, India

Who is Shruthi Ls? Overview

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Shruthi Ls is listed as EDA Tool Development | PDK Development | AMS Layout Design | Design Flow Automation | VLSI | Semiconductors | Silicon at HCLTech, based in Bengaluru, Karnataka, India. AeroLeads shows a matched LinkedIn profile for Shruthi Ls.

Shruthi Ls previously worked as Technical Lead at Hcltech and Senior Engineer - R&D at Pravarta Labs Llp. Shruthi Ls holds Master Of Technology (M.Tech.), Electronics And Communications Engineering from Visvesvaraya Technological University.

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HCLTech

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About Shruthi Ls

Semiconductor-VLSI professional with 7 years of hands-on experience in EDA Tool Development, Analog Layout Automation, PDK (Process Design Kit) Development, Design Flow Automation and Analog & Mixed Signal Layout Design. I have been successful in delivering excellence in all the assignments I have undertaken. I am a strong team player, handled team of 10 engineers, possess strong communication skills, quick learner and always ready to take up challenges and deliver success. My interest areas include PDK development and EDA tool development. Always looking for opportunities where my expertise, experience and skills are well utilized, wherein I can create maximum impact for the organization and teams I work with and grow together.

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Shruthi Ls's current company

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HCLTech
Hcltech
EDA Tool Development | PDK Development | AMS Layout Design | Design Flow Automation | VLSI | Semiconductors | Silicon
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5 roles

Shruthi Ls work experience

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Technical Lead

Current

Bengaluru, Karnataka, India

  • Project: Automation for IP view generation
  • Ensuring correctness of Standard Cell IP/GPIO Libraries by comparing OA and- GDS using LVL, LVS & SVS checks with SKILL and Python
  • Verifying inhouse flows for Library View generation for Std Cell Ips provided byTSMC for final validation of views generated by checking all the logs generated.
  • Working on TSMC 2nm, 3nm, 5nm,7nm, technology nodes.
  • Leading a team of 10 engineers for this activityProject: Automation for extracting… Show more Project: Automation for IP view generation
  • Leading a team of 10 engineers for this activityProject: Automation for extracting Schematic hierarchical nets and Device Properties
Aug 2023 - Present

Senior Engineer - R&D

Bangalore Urban, Karnataka, India

  • PDK (Process Design Kit) Development:
  • Developed Physical Verification Design Rule Deck using SVRF (Standard Verification Rule Format) In Assura and PVS.
  • Working on Physical Verification Layout vs Schematic (LVS) in PVS.
  • Developed LDMOS PCELLS with CDF and CDF callback using SKILL scripts.
  • Developed custom SKILL script of metal rectangle creation for fill based on the boundary box selected by the user.EDA Tool Development:Power Device Generator (PDG) – Development… Show more PDK (Process Design Kit).
  • Developed custom SKILL script of metal rectangle creation for fill based on the boundary box selected by the user.EDA Tool Development:Power Device Generator (PDG) – Development of user-friendly tool to generate.
Jul 2019 - Jul 2023

Engineer R&D

Bengaluru, Karnataka, India

  • Analog and Mixed Signal Layout Design:
  • Worked on various block level projects – Single Stage Amplifier, Resistor Ladder, Capacitor Array and Low dropout regulator.
  • Hands on experience in area estimation, floorplan & layout implementation of resistor divider network, protection circuits and custom digital circuits.
  • Well versed with matching of differential pairs, current mirrors, resistor network array, area optimization, minimizing parasitics and routing considering the current… Show more Analog and Mixed Signal Layout Design:
  • Well versed with matching of differential pairs, current mirrors, resistor network array, area optimization, minimizing parasitics and routing considering the current density.
  • Actively participated in the layout reviews & carried out necessary modifications/improvements in the layout.
Oct 2017 - Jun 2019

Freelance Tutor

Freelance

Bengaluru, Karnataka, India

Coaching for High school students in Mathematics, Physics and Chemistry

Apr 2016 - Sep 2017

Research Intern

Bengaluru, Karnataka, India

  • Development of USB based Data Acquisition System using Actel FPGA
  • Acquiring the data from the external world with respect to clock to the FPGA through FTDI FT232
  • Roles and responsibilities: Writing of requirements document, Programming the Kit, Writing Test Benches and bug fixing. Tools: MicrosemiLiberoSoC + Modelsim 10.3c.
Jul 2015 - Jan 2016
2 education records

Shruthi Ls education

FAQ

Frequently asked questions about Shruthi Ls

Quick answers generated from the profile data available on this page.

What company does Shruthi Ls work for?

Shruthi Ls works for HCLTech.

What is Shruthi Ls's role at HCLTech?

Shruthi Ls is listed as EDA Tool Development | PDK Development | AMS Layout Design | Design Flow Automation | VLSI | Semiconductors | Silicon at HCLTech.

Where is Shruthi Ls based?

Shruthi Ls is based in Bengaluru, Karnataka, India while working with HCLTech.

What companies has Shruthi Ls worked for?

Shruthi Ls has worked for Hcltech, Pravarta Labs Llp, Freelance, and Raman Research Institute.

How can I contact Shruthi Ls?

You can use AeroLeads to view verified contact signals for Shruthi Ls at HCLTech, including work email, phone, and LinkedIn data when available.

What schools did Shruthi Ls attend?

Shruthi Ls holds Master Of Technology (M.Tech.), Electronics And Communications Engineering from Visvesvaraya Technological University.

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