Evgeny Shumsky Email & Phone Number

Developing an innovative, blazing high performance solution for flash storage.

Definition, architecture and implementation of FPGA based solution for ultra low latency network device, capable of 8*10G line rate full TCP/UDP termination, 7 layer deep packet inspection, classification and tick to trade flow. Product is deployed and successfully used.

Responsible for architecture of various units used in switch / router ASICs, like hardware dynamic memory management, data modification unit with multi-level tunneling, L2-L4 header modification, sniffering, NAT capabilities, distributed shared memory unit, 1G - 100G multi-client DMA engines, packet reassembly engine and other.

As a part of next generation hardware architecture team I was responsible for defining data path of multi-core switch / router architecture with shared memory. The most valuable contribution was scalable memory management for multi-core device, shared memory for multi-core device, high performance multi-speed DMA engines, task order maintaining unit for multi-core device and other. Responsible for a group of 10 engineers.

Responsible for the backend flow of complicated macros that include number of clock domains, sub-macros and high frequency. Responsible for all backend aspects from synthesis to timing closure through place and route and clock tree synthesis. Defined and developed a significant decrease in number of clocks in a multi-clock macro, extremely simplifying and shortening backend efforts. Responsible for outsourcing backend team.

Responsible for definition and implementation of simulation environments for the switches and routers developed in Marvell/Galileo. Those simulation environments include definition and development of peripheral elements, diagnostic elements and checkers, and also user interfaces.