Siddhant Gupta Email & Phone Number

California, United States

Working on silicon for XR applications

Cupertino, California, United States

Microarchitecture and RTL design, formal verification, supporting design verification for bring-up, synthesis + timing closure, and power/performance/area optimization experiments for novel pixel-processing blocks in in the display subsystem of Apple Silicon.

Los Angeles Metropolitan Area

PI: Professor Richard Wesel, PhDResearch Area: Communication Systems

PI: Professor Nader Sehatbakhsh - Electrical and Computer EngineeringResearch Area: Secure Computing Systems- Worked on hardware trojan detection for AES encryption circuits by modeling the physical side channels from RTL on an Altera Quartus DE0-CV board- Used Verilog in Quartus Prime to program the FPGA to investigate effect from different hardware components on EM side channels- Automated measurements and data processing using Keysight's IVI-C drivers with MATLAB to process data from an oscilloscope and spectrum analyzer.

Los Angeles Metropolitan Area

PI: Professor Lei He - Department of Electrical and Computer EngineeringResearch Area: AI on a Chip- Worked with graduate students to transition OPU AI accelerator to a systolic-array based architecture- Designed processing element for systolic arrays at the RTL level in System-Verilog and performed verification

Los Angeles Metropolitan Area

President of the largest ECE organization on campus, leading an officer board of almost 30 serving over 300 members with technical projects, mentorship, workshops, and socials. IEEE at UCLA is one of the largest and most active student branches of IEEE in the world, recognized for excellence at a national level.

Los Angeles Metropolitan Area

Developed and held a series of technical workshops for undergraduate students. Topics included soldering, PCB Design (EAGLE), MATLAB, Linux, MCUs, Verilog and FPGAs

Los Angeles Metropolitan Area

Cupertino, California, United States

• Defined microarchitecture for HEVC/AVC fractional sample interpolation modules in the Apple Video Encoder subsystem of the SoC• Performed Power, Performance, Area optimizations in Verilog, debugged using Verdi and Indago, and wrote coverage properties and assertions• Supported design verification team from initial bring‑up of modules to ensuring functional coverage for the design

Master Of Science - Ms, Electrical Engineering

Bachelor Of Science - Bs, Computer Engineering, (Gpa) 3.93

Focus in Computer Architecture and Embedded Systems

High School Diploma

Activities and Societies: Mock Trial, Model UN, Newspaper, mgh Physics, Swim and Dive, CSF