Principal Electrical Design Engineer
Current• Designing microchips on Logic Probe Card Substrate (Organic and Ceramic) designs, including creating netlists, planning BGA floor layouts, and arranging 46-72 layer stack-up planning. • Reviewing physical layouts using Cadence Allegro.• Working on process development for Vertical Probe Cards technology• Driving design automation to fully automate the Substrate logical design process, helping improve design quality and efficiency.• Supporting major customers in the semiconductor industry for the probe card projects for their developing technology.