Siddharth Potbhare Email & Phone Number

College Park, Maryland, US

As CEO of Untethered Labs, I am leading the efforts for rapid commercialization of GateKeeper technology (www.gkaccess.com). It is an extremely user friendly hardware+software method for ensuring security and privacy of individual work stations in small and large businesses. We are actively seeking investment and partnerships with angel investors who are.

College Park, MD, US

Principal investigator on several DOD, NASA and NSF research programs on various technologies including silicon carbide, long-wave infrared detectors, cryogenic electronics.Helped raise more than $5M in R&D funding from various government agencies including NSF, NASA, US Army, US Navy.Product development team leader for several consumer products –.

Technology lead for the SunFriend UV Monitor: Lead the design efforts for SunFriend including the current and future generations of SunFriend UV Monitor, hardware, firmware, software, product engineering, and app development.Representative of CoolCAD Electronics on the SunFriend boardAdvise CEO of SunFriend in negotiations with investors, distributors.

Gaithersburg, MD, US

Modeling and simulation of tunneling-FET transistors at NIST, GaithersburgModeling source/drain series resistance in ultra-scaled CMOS devicesGenerating ITRS roadmap for CMOS device technology for 2012 and 2013 as part of the Process Integration Devices and Structures (PIDS) group in ITRS

College Park, MD, US

College Park, MD, US

• Semiconductor Simulation LaboratoryAdvisor: Dr. Neil Goldsman Collaboration: U.S. Army Research Laboratory, Adelphi, MDProject: Physics based numerical modeling and characterization of Silicon Carbide (SiC) high.
• Designed a custom 2-D Drift Diffusion device simulator for SiC MOSFETs
• Developed models for surface roughness, interface trap, and surface phonon scatterings, high field saturation velocity, temperature dependence of interface traps and incomplete ionization
• Characterized the high temperature operation of SiC MOS devices and identified interface traps and surface roughness as the dominant performance degradation mechanisms
• Modeled impact ionization related breakdown for high power 4H-SiC DMOSFETs
• Actively interacted with researchers at University of Maryland, U.S. ARL and NIST

Gaithersburg, MD, US

• Supervisor: Dr. John SuehleProject: Measurement of ultra-fast current transients in SiC MOSFETs
• Measured sub-microsecond current transients in 4H-SiC MOSFETs by designing fast current measurement circuits
• Characteristic transient current overshoot behavior was observed and was attributed to finite time response of interface, near-interface and oxide traps
• Developed a time dependent trap occupation model and simulated the transient behavior of SiC MOSFETs to extract the energy-dependent trap capture cross-sections
• Tools used: Probe station, semiconductor parameter analyser (4155), digital storage oscilloscope, ORCAD Spice for circuit design and optimization, Eagle Layout for PCB design

Phd, Electrical Engineering - Semiconductor Devices

Ms, Electrical Engineering - Microelectronics

Be, Electronics