Siddharth Ravikumar Email & Phone Number

Sunnyvale, California, US

• Work with Technical account manager and world-wide account teams for forming strategies and successfully driving Synopsys tools inside customer projects to enable business success for Synopsys
• Liaison with RnD Engineering, Sales and Customers to develop clear product requirement specifications for new features and flows that align with the product vision
• Support customers promptly and effectively to improve customer productivity and satisfaction with Synopsys’ simulation products
• Provide Demos, training and technical support to customers using Synopsys Verification tools such as VCS-MX,verdi3 and VIPs
• Involve and drive the Tool evaluation/benchmark, Methodology review; Tool deployment and adoption; drive competitive replacements
• Take ownership of one or more strategic accounts and/or business/technology initiatives for strategic and tactical business needs

• Lead teamof 7 members on the development and maintenanceof the Gate Level Simulation Methodology at Intel.
• Work closely with cross functional teams such as Design team, formal verification team and physical design team
• Find the root cause of test failures and provide the necessary solutions
• Scripting in PERL and PYTHON to improve verification performance by automating existing flow
• Create documentation on the methodology developed
• Set Business objectives and provide weekly status to Intel on behalf of the team.

San Jose, CA, US

• Silicon verification on a UVM environment for high end Class D Speaker/headphone Amplifiers with I/V Sense used in smartphones and tablets. Completed 4 tape outs.
• Developed detailed test plan for each user mode. Wrote 30+ tests to verify circuit correctness, full chip functionality, and coverage for each user mode scenario.
• Isolated many critical bugs in the design using the random verification and running regressions.
• Built and implemented more flexible and automated models, reducing design analysis time by 50%
• Responsible for running full chip RTL, Gate and Post synthesis regressions and related test case debug. Regressions are run for any single change in RTL and assembly.
• Worked on Cadence’s EMANAGER for extensive coverage analysis and verification planning

San Jose, CA, US

-  Developed an innovative in-house functional verification tool built to reduce load board revisions, thereby reducing cost and cycle time. The tool performed a system Verilog /Verilog-ams simulation on the Verilog net-list of the schematic to find connectivity and functional errors on the load board before sending it to the fab.  Developed the system.

US

-Test Vector Creation for High speed DDR2, DDR3 memory modules-Post Silicon Debug Activities for Logic Devices Incs latest memory products on Agilent 93000 test platform.-Test/Quality hardware integrity/Continuity Verification-Device characteristics measurements for DDR2/DDR3 product lines using Lab instruments.-PERL/Shell script for Production data log.

Santa Clara, CA, US

Mentored and conducted Lab sessions for undergraduate students for the following courses1.Digital Signal Processing 2.Advance Logic Design 3.DSP System Architecture 4. Electronic circuits

Santa Clara, CA, US

Part of a research group that explores the different speech coding techniques. I worked on waveform substitution techniques for missing packets in voice communication through pitch detection and pattern matching techniques.Currently working on the Matlab Implementation of the WSOLA (waveform similarity based overlap and add) algorithm

IN

Interned for three months at India’s largest telecom company at the end of my sophomore year where I was exposed to several mobile technologies and gave me an insight into how CDMA, GSM and GPRS work.Also learnt about the various switching techniques in wired communication.

Ms, Electrical Engineering

Bs, Electronics And Communication