Ben Chia Email & Phone Number

High Speed interconnect design, modeling and measurements

1900 Wyatt Dr. #9, Santa Clara, CA 95054

Signal Integrity Modeling, Correlation, Measurement and Validation.

1900 Wyatt Dr, Santa Clara CA 95054

Package design, Signal Integrity System Model and Simulation, Connector, Cable, PCB characterization. RF probe and probe station developmentSignal Integrity Test and Measurement Seminar

San Jose

memory channel simulation, package design, gigabit connector characterization, test fixture design

High speed memory subsystem modeling, parallel bus, PCB layout, package stackup, connector crosstalk. 20G high speed SerDe backplane, line card simulation, modeling and measurement. Agilent 110G VNA microprobing lab setup. Interconnect fixture deisgn. PCB impedance control, TDR calibration

Engineering: 10+ years of high speed system engineering design experiencedDesigned Intel 800Mbps Castine flip chip package, propose PCB design rule Designed Toshiba wire bond DDR3 controller package and perform short channel simulationProvided 2D/3D and measurement based models for package, PCB and connectorsCorrelated 10Gbps crosstalk model for CISCO.

Memory subsystem project lead for Spark Compatible server - determine memory architecture - select memory technology and IO interface - performance analysisSignal Integrity staff for high speed router - Fujitsu flip chip package design - specify high speed link IO design, testing and verification

Technology Staff and Main Memory Project LeadDesigned the main memory system of Sun Micro compatible server systemDesigned the crossbar switch chip floor plan, package design and interconnect analysis

Memory subsystem interconnect design, memory technology selection and high speed switch IO testing and measurement

Master

Master