Research Development Software Engineer
CurrentResponsibilities:-Research on implementing Deep Learning Algorithm on Power & Area (PPA) Estimation on Network On Chip (NOC)-Responsible to flush through all RTLs on NOC using Synopsys Compiler to ensure synthesizable, quality control, and bugs catch-Responsible to define and maintain features & spec owned in SAS-Completed analytical model with up to 90% accuracy to estimate power and area on NOC within 2 months of given timeline-Design and implemented automated data collection workflow on PD synthesis within 1 month of given timeline-Design and integrated data collection & modelling automation architecture within 3 months of given timelineExperience:- C++, Python, TCL (.tcl), Shell Script (.sh)-Jenkins, Jira, Gerrit, Git- AMBA protocol exposure (AXI, ACE, CHI)- RAPTuner Development, Design Software Architecture Specifications (SAS), Spec & Feature Owner- Coherent/Non-Coherent Network-on-Chip (NoC)- Synopsys DC Compiler & IC Compiler, Physical Design Workflow (synthesis, auto-place & route, SDC)