Simon Goble Email & Phone Number

Newark, California

Mountain View, Ca

Develop MATLAB scripts for camera silicon analog path corner testing. Code C-model for pixel processing on SIMD processor. Assist with RTL/testbench validation. Build unit-test suite for SIMD instruction set.

Milpitas, Ca

FPGA Verification. Adapt and partition existing ASIC RTL to build multi-FPGA verification platforms on Xilinx and Altera boards. Develop wide multiplexed interconnect busses between FPGAs. Support design & RTL verification teams with early detection of coding/synthesis issues. Enable pre-silicon software development giving a time-to-market advantage. Early adopter of Synopsys Synplicity System Verilog synthesis.

Cupertino

Verilog module design for direct-to-CD audio recorder. Synthesized for FPGA emulation and IC. Administered board layout vendors. Factory-floor digital/audio quality test suite. Designed in-car video recording system. Supervised keyboard/display design.

Mountain View, Ca

JPEG Image compression on dual-DSP Apple NuBus board. Significantly optimize code to outperform native CPU and enhance quality. Develop DSP code for Adobe PhotoShop filter plugins. Develop and implement quality image rotation algorithm for pipelined operation. Redesigned smaller NuBus boards, cost-reduced and brought to production. Developed boards for Sun, VME & PC.Supported image scanner product hardware and printing software in Windows.Designed Verilog timing generator for image scanner IC.