Running the Software Development team responsible for developing core software for the JN51xx family of low power IEEE802.15.4 Wireless Microcontrollers. Working in close cooperation with other business stakeholders, such as Marketing, ASIC Design and field support teams to ensure software is delivered as a fully integrated systems solution. Accountable for delivering and maintaining SDK’s for devices such as JN5148, JN5164/68/69, JN5179, JN5189/88 and K32W041/61, covering… Show more Running the Software Development team responsible for developing core software for the JN51xx family of low power IEEE802.15.4 Wireless Microcontrollers. Working in close cooperation with other business stakeholders, such as Marketing, ASIC Design and field support teams to ensure software is delivered as a fully integrated systems solution. Accountable for delivering and maintaining SDK’s for devices such as JN5148, JN5164/68/69, JN5179, JN5189/88 and K32W041/61, covering IEEE802.15.4 wireless protocol stacks such as, JenNet-IP, Zigbee 3.0, Zigbee HA, Zigbee LL and Zigbee Smart Energy. Project Manager for JN51xx SDK software releases, software enablement for new devices and wireless protocol developments. Show less

Accepted additional responsibility of Site Manager for the Sheffield office, including site health and safety, admin, IT planning, office maintenance, purchasing, shipping & export compliance.

Continued in the Software Verification Manager role following acquisition of the Jennic business by NXP, maintaining responsibility for the testing and quality control of JN51xx software SDK releases. Focused on extending the verification activities to new wireless software stacks and JN51xx devices, while aligning verification processes into NXP’s existing development flow. Supported the bring-up of a new offshore wireless software team to increase wireless software capacity… Show more Continued in the Software Verification Manager role following acquisition of the Jennic business by NXP, maintaining responsibility for the testing and quality control of JN51xx software SDK releases. Focused on extending the verification activities to new wireless software stacks and JN51xx devices, while aligning verification processes into NXP’s existing development flow. Supported the bring-up of a new offshore wireless software team to increase wireless software capacity, transitioning parts of the Zigbee software verification activities. Headed the development of the JN514x-EK040 and JN516x-EK001 Development/Evaluation Kits. Show less

Tasked with creating a software verification team from the ground up for testing of software developed around the Jennic family of low-power IEEE802.15.4 Wireless Microcontrollers.Pioneered the software verification strategy for JN51xx wireless devices and instigated processes for SDK build configuration, tagging policies, bug tracking etc.Drove the development of novel test infrastructure, including multi-node regression frameworks, test hardware platforms, test specifications,… Show more Tasked with creating a software verification team from the ground up for testing of software developed around the Jennic family of low-power IEEE802.15.4 Wireless Microcontrollers.Pioneered the software verification strategy for JN51xx wireless devices and instigated processes for SDK build configuration, tagging policies, bug tracking etc.Drove the development of novel test infrastructure, including multi-node regression frameworks, test hardware platforms, test specifications, reporting and definition of KPI’s. Oversaw the creation of several self-checking regression suites for IEEE802.15.4 MAC, JenNet, RF4CE and ZigbeePro networking stacks, 6LowPAN/JenNet-IP, Zigbee Home Automation, Light Link and Smart Energy application layers and unit test of smaller generic framework modules and hardware abstraction layers. Show less

Owner of the RTL IP-cores business. Responsibilities included business development, license negotiation, customer liaison and technical design-in support from initial engagement through chip bring-up. The Wireline IP-core portfolio includes ATM-SAR, Forward Error Correction (FEC) and Serial RapidIO IP cores licensed through Semiconductor foundry IP programs, such as from IBM and TI, and directly to Tier 1 Telecom OEM’s.Oversaw the evaluation and selection of a new CPU core for… Show more Owner of the RTL IP-cores business. Responsibilities included business development, license negotiation, customer liaison and technical design-in support from initial engagement through chip bring-up. The Wireline IP-core portfolio includes ATM-SAR, Forward Error Correction (FEC) and Serial RapidIO IP cores licensed through Semiconductor foundry IP programs, such as from IBM and TI, and directly to Tier 1 Telecom OEM’s.Oversaw the evaluation and selection of a new CPU core for future JN51xx devices. Worked closely with a new start-up supplier to ensure the quality of the IP deliverables and first-time right silicon in its inaugural device, the JN5148. Show less

Architect for the modular ATM-SAR (Asynchronous Transfer Mode - Segmentation & Reassembly) and Serial RapidIO High Speed interface IP cores.Responsible for the overall system architecture for the cores, module design and verification specifications. Cores defined from the outset to be modular, with build-time configurable options to allow users to tailor cores for their target application, trading off functionality and resource levels against core area, with options for different host… Show more Architect for the modular ATM-SAR (Asynchronous Transfer Mode - Segmentation & Reassembly) and Serial RapidIO High Speed interface IP cores.Responsible for the overall system architecture for the cores, module design and verification specifications. Cores defined from the outset to be modular, with build-time configurable options to allow users to tailor cores for their target application, trading off functionality and resource levels against core area, with options for different host interfaces and target technologies. Led the Engineering design teams through the development of the IP cores and personally worked on several of the key RTL modules including AHB, PCI and PLB host interfaces. Also responsible for the creation of support collateral for the cores, such as product briefs, datasheets and application notes.Supported the Business Development activity, working directly with clients during initial engagements to provide integration guidance into their overall product architecture. Support continued through design in process, through tape-out, chip bring-up and field support. During development of the Serial Rapid IO IP core actively participated in the SRIO standards bodies, including attending plug fest interop events and marketing roadshows. Show less

Employed as a Design Consultant undertaking digital ASIC design services projects for 3rd party clients. Working from project definition, through RTL design, verification and synthesis to delivery including generation of user documentation.Engagements typically involved working closely with clients to extract detailed requirements for a project in order to generate detailed specifications, list of deliverables, work breakdown structures and acceptance criteria. Completed a… Show more Employed as a Design Consultant undertaking digital ASIC design services projects for 3rd party clients. Working from project definition, through RTL design, verification and synthesis to delivery including generation of user documentation.Engagements typically involved working closely with clients to extract detailed requirements for a project in order to generate detailed specifications, list of deliverables, work breakdown structures and acceptance criteria. Completed a series of ATM SAR AAL-1 co-processor projects for the research arm of a Tier 1 OEM. Show less

Digital RTL Design Engineer developing large standard cell and gate array ASIC's for the Telecommunications market. Working from system specifications, tasks involved system de-composition, digital module design; RTL capture (VHDL and Verilog) and simulation; verification and debug; synthesis; layout.Gained extensive experience of modelling at or gate level, in both, working on a number of ATM and GSM devices, test benches, simulation models and configurable IP cores.… Show more Digital RTL Design Engineer developing large standard cell and gate array ASIC's for the Telecommunications market. Working from system specifications, tasks involved system de-composition, digital module design; RTL capture (VHDL and Verilog) and simulation; verification and debug; synthesis; layout.Gained extensive experience of modelling at or gate level, in both, working on a number of ATM and GSM devices, test benches, simulation models and configurable IP cores. Served as part of a methodologies group providing CAE tool support to other internal design teams, including beta testing for the CAE Tool suppliers. Developed an optimised hardware-software shared memory interface deployed in the MB86698 FireStream ATM SAR family of devices. Show less